SLLSF92A February   2019  – March 2019 TUSB8044A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 I2C Programming Support Using Internal HID to I2C Interface
        1. 8.3.3.1 SET REPORT (Output)
        2. 8.3.3.2 GET REPORT (Feature)
        3. 8.3.3.3 GET REPORT (Input)
      4. 8.3.4 USB2.0 Billboard
      5. 8.3.5 One Time Programmable (OTP) Configuration
      6. 8.3.6 Clock Generation
      7. 8.3.7 Crystal Requirements
      8. 8.3.8 Input Clock Requirements
      9. 8.3.9 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
        1. Table 10. Bit Descriptions – ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
        1. Table 11. Bit Descriptions – Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
        1. Table 12. Bit Descriptions – Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
        1. Table 13. Bit Descriptions – Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
        1. Table 14. Bit Descriptions – Product ID MSB Register
      7. 8.5.7  Device Configuration Register
        1. Table 15. Bit Descriptions – Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
        1. Table 16. Bit Descriptions – Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
        1. Table 17. Bit Descriptions – Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
        1. Table 18. Bit Descriptions – Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
        1. Table 19. Bit Descriptions – Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
        1. Table 20. Bit Descriptions – USB 2.0 Port Polarity Control Register
      13. 8.5.13 Billboard AlternateModeVdo
        1. Table 21. Bit Descriptions – Billboard AlternateModeVdo
      14. 8.5.14 UUID Registers
        1. Table 22. Bit Descriptions – UUID Byte N Register
      15. 8.5.15 Language ID LSB Register
        1. Table 23. Bit Descriptions – Language ID LSB Register
      16. 8.5.16 Language ID MSB Register
        1. Table 24. Bit Descriptions – Language ID MSB Register
      17. 8.5.17 Serial Number String Length Register
        1. Table 25. Bit Descriptions – Serial Number String Length Register
      18. 8.5.18 Manufacturer String Length Register
        1. Table 26. Bit Descriptions – Manufacturer String Length Register
      19. 8.5.19 Product String Length Register
        1. Table 27. Bit Descriptions – Product String Length Register
      20. 8.5.20 Device Configuration Register 3
        1. Table 28. Bit Descriptions – Device Configuration Register 3
      21. 8.5.21 USB 2.0 Only Port Register
        1. Table 29. Bit Descriptions – USB 2.0 Only Port Register
      22. 8.5.22 Billboard SVID LSB
        1. Table 30. Bit Descriptions – Billboard SVID LSB
      23. 8.5.23 Billboard SVID MSB
        1. Table 31. Bit Descriptions – Billboard SVID MSB
      24. 8.5.24 Billboard PID LSB
        1. Table 32. Bit Descriptions – Billboard PID LSB
      25. 8.5.25 Billboard PID MSB
        1. Table 33. Bit Descriptions – Billboard PID MSB
      26. 8.5.26 Billboard Configuration
        1. Table 34. Bit Descriptions – Billboard Configuration.
      27. 8.5.27 Billboard String1 Length
        1. Table 35. Bit Descriptions – Billboard String1 Length.
      28. 8.5.28 Billboard String2 Length
        1. Table 36. Bit Descriptions – Billboard String2 Length.
      29. 8.5.29 Serial Number String Registers
        1. Table 37. Bit Descriptions – Serial Number Registers
      30. 8.5.30 Manufacturer String Registers
        1. Table 38. Bit Descriptions – Manufacturer String Registers
      31. 8.5.31 Product String Registers
        1. Table 39. Bit Descriptions – Product String Byte N Register
      32. 8.5.32 Additional Feature Configuration Register
        1. Table 40. Bit Descriptions – Additional Feature Configuration Register
      33. 8.5.33 SMBus Device Status and Command Register
        1. Table 41. Bit Descriptions – SMBus Device Status and Command Register
      34. 8.5.34 Billboard String1_2
        1. Table 42. Bit Descriptions – Billboard String1_2
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Upstream Port Implementation
          2. 9.2.1.2.2  Downstream Port 1 Implementation
          3. 9.2.1.2.3  Downstream Port 2 Implementation
          4. 9.2.1.2.4  Downstream Port 3 Implementation
          5. 9.2.1.2.5  Downstream Port 4 Implementation
          6. 9.2.1.2.6  VBUS Power Switch Implementation
          7. 9.2.1.2.7  PD Controller and EEPROM Implementation
          8. 9.2.1.2.8  DisplayPort Implementation
          9. 9.2.1.2.9  Clock, Reset, and Misc
          10. 9.2.1.2.10 TUSB8044A Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8044A Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB8044A differential pairs: USB_DP_XX, USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.

  1. Must be designed with a differential impedance of 90 Ω ±10%.
  2. In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each pair should be separated by at least 5 times the signal trace width. Separating with ground as depicted in the layout example will also help minimize cross talk.
  3. Route all differential pairs on the same layer adjacent to a solid ground plane.
  4. Do not route differential pairs over any plane split.
  5. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes stub on the differential pair.
  6. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
  7. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for SS differential pair signals and USB 2.0 differential pair signals is eight inches. Longer trace lengths require very careful routing to assure proper signal integrity.
  8. Match the etch lengths of the differential pair traces (i.e. DP and DM or SSRXP and SSRXM or SSTXP and SSTXM). There should be less than 5 mils difference between a SS differential pair signal and its complement. The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.
  9. The etch lengths of the differential pair groups do not need to match (i.e. the length of the SSRX pair to that of the SSTX pair), but all trace lengths should be minimized.
  10. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure that the same via type and placement are used for both signals in a pair. Any vias used should be placed as close as possible to the TUSB8044A device.
  11. To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be routed to SSTXM or SSRXM can be routed to SSRXP.
  12. To ease routing of the USB2 DP and DM pair, the polarity of these pins can be swapped. If this is done, the appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4, must be set.
  13. Do not place power fuses across the differential pair traces.