SLLSE67I March   2011  – March 2016 TUSB9261

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics for 3.3-V Digital I/O
    6. 6.6 SuperSpeed USB Power Consumption
    7. 6.7 High-Speed USB Power Consumption
    8. 6.8 Oscillator Specification
    9. 6.9 Crystal Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
        1. 7.3.1.1 General Functionality
        2. 7.3.1.2 Firmware Support
        3. 7.3.1.3 GPIO/PWM LED Designations
        4. 7.3.1.4 Power-Up and Reset Sequence
      2. 7.3.2 Clock Connections
        1. 7.3.2.1 Clock Source Requirements
        2. 7.3.2.2 Clock Source Selection Guide
    4. 7.4 Device Functional Modes
      1. 7.4.1 VBUS Power
      2. 7.4.2 External Power
      3. 7.4.3 External Voltage Regulator
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 PWM Terminals
        2. 8.2.2.2 JTAG Interface
        3. 8.2.2.3 Voltage Regulator Schematic
        4. 8.2.2.4 SPI
  9. 9 Power Supply Recommendations
    1. 9.1 Digital Supplies 1.1-V and 3.3-V
    2. 9.2 Analog Supplies 1.1-V and 3.3-V
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 High-Speed Differential Routing
      2. 10.1.2 SuperSpeed Differential Routing
      3. 10.1.3 SATA Differential Routing
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)
MIN MAX UNIT
VDD Steady-state supply voltage –0.3 1.4 V
VDD33/
VDDA33		 Steady-state supply voltage –0.3 3.8 V
Tstg Storage temperature –55 150 °C

6.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) ±2000 V
Charged device model (CDM), per JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Digital 1.1-V supply voltage 1.045 1.1 1.155 V
VDD33 Digital 3.3-V supply voltage 3 3.3 3.6 V
VDDA33 Analog 3.3-V supply voltage 3 3.3 3.6 V
VBUS Voltage at VBUS PAD 0 1.155 V
TA Operating free-air temperature range 0 70 °C
Industrial version –40 85
TJ Operating junction temperature range –40 100 °C

6.4 Thermal Information

THERMAL METRIC(1) TUSB9261 UNIT
PVP (HTQFP)
64 PINS
RθJA Junction-to-ambient thermal resistance 30.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.0 °C/W
RθJB Junction-to-board thermal resistance 6.1 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 6.1 °C/W
RJθC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics for 3.3-V Digital I/O

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
TR Rise time 5 pF 1.5 ns
TF Fall time 5 pF 1.53 ns
IOL Low-level output current VDD33 = 3.3 V, TJ = 25°C 6 mA
IOH High-level output current VDD33 = 3.3 V, TJ = 25°C –6 mA
VOL Low-level output voltage IOL = 2 mA 0.4 V
VOH High-level output voltage IOL = –2 mA 2.4 V
VO Output voltage 0 VDD33 V
RECEIVER
VI Input voltage 0 VDD33 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2 V
Vhys Input hysteresis 200 mV
tT Input transition time (TR and TF) 10 ns
II Input current VI = 0 V to VDD33 5 µA
CI Input capacitance VDD33 = 3.3 V, TJ = 25°C 0.384 pF

6.6 SuperSpeed USB Power Consumption

POWER RAIL TYPICAL ACTIVE CURRENT (mA)(1) TYPICAL SUSPEND CURRENT (mA)(2)
VDD11 291 153
VDD33(3) 65 28
(1) Transferring data by SS USB to a SSD SATA Gen II device. No SATA power management, U0 only.
(2) SATA Gen II SSD attached no active transfer. No SATA power management, U3 only.
(3) All 3.3-V power rails connected together.

6.7 High-Speed USB Power Consumption

POWER RAIL TYPICAL ACTIVE CURRENT (mA)(1) TYPICAL SUSPEND CURRENT (mA)(2)
VDD11 172 153
VDD33(3) 56 28
(1) Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management.
(2) SATA Gen II SSD attached no active transfer. No SATA power management.
(3) All 3.3-V power rails connected together.

6.8 Oscillator Specification

XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground plane. A 40-MHz clock can be used.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CXI XI input capacitance TJ = 25°C 0.414 pF
VIL Low-level input voltage 0.7 V
VIH High-level input voltage 1.05 V
Ttosc_i Frequency tolerance Operational temperature –50 50 ppm
Tduty Duty cycle 45% 50% 55%
TR/TF Rise/fall time 20% to 80% 6 ns
RJ Reference clock JTF (1 sigma)(1)(2) 0.8 ps
TJ Reference clock JTF (total p-p)(2)(3) 25 ps
Tp-p Reference clock jitter (Absolute p-p)(4) 50 ps
(1) Sigma value assuming Gaussian distribution
(2) After application of JTF
(3) Calculated as 14.1 × RJ + DJ
(4) Absolute phase jitter (p-p)

6.9 Crystal Specification

A parallel, 20-pF load capacitor should be used if a crystal source is used. VSSOSC should not be connected to the PCB ground plane. A 40-MHz crystal can be used.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Oscillation mode Fundamental
ƒO Oscillation frequency 40 MHz
ESR Equivalent series resistance 40 MHz 50 Ω
Ttosc_i Frequency tolerance Operational temperature ±50 ppm
Frequency stability 1 year aging ±50 ppm
CL Load capacitance 12 20 24 pF
CSHUNT Crystal and board stray capacitance 4.5 pF
Drive level (max) 0.8 mW