SLDS250A December   2019  – May 2022 TUSS4440

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power-Up Characteristics
    6. 6.6  Transducer Drive
    7. 6.7  Receiver Characteristics
    8. 6.8  Echo Interrupt Comparator Characteristics
    9. 6.9  Digital I/O Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excitation Power Supply (VDRV)
      2. 7.3.2 Burst Generation
        1. 7.3.2.1 Burst Generation Diagnostics
      3. 7.3.3 Transformer Transducer Drive
      4. 7.3.4 Analog Front End
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 REG_USER Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Transformer Drive Configuration Options
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
          4. 8.2.1.2.4 Transformer Turns Ratio
          5. 8.2.1.2.5 Transformer Saturation Current and Main Voltage Rating
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

The device has four functional modes:

    Sleep ModeUltra-low current consumption sleep mode

    In this mode, all major blocks of the device are disabled, including VDRV regulation. The SPI interface is still active. This transition into and out of this mode is done using the SLEEP_MODE_EN register bit. Upon issuing a command to exit this mode, the device transitions to other modes only when the VDRV pin reaches the programmed regulation voltage.

    Standby ModeLow current standby mode

    In this state, the VDRV regulation is active, but other analog blocks are shut down to reduce quiescent current consumption. The STDBY_MODE_EN bit is used to enter and exit this mode through SPI. The device can transition very quickly from this state to one of the active states for bursting and listening.

    Listen ModeDefault mode of the device

    This is the default mode of the device when it is not in Sleep mode or Standby mode. In this mode, there is no activity on the transmitter block and the device is actively listening for any ultrasonic signals.

    Burst ModeMode in which the device is enabled to start a burst to drive the transducer

    In this mode, the transmitter blocks are active and enabled to drive the transducer depending on when the start of burst occurs. The receiving path is also active at the same time listening for signals at the input. This mode is entered when a burst enable event occurs and exited when an end of burst occurs as described in Section 7.3.2 section.

Figure 7-7 shows an example of the transitions between the different modes of the device for IO_MODE = 0, where the burst is activated through a SPI command and end of burst occurs as the number of programmed pulses are sent.

GUID-D2B5EFDC-9804-4D70-B6EA-9F46523C7544-low.gifFigure 7-7 Device Modes Timing Diagram
Note:
  • The transition to standby or active mode (listen or burst) from power-up or sleep mode is done only once the VDRV voltage crosses the programmed VDRV_VOLTAGE_LEVEL bit, or is higher 64 ms, whichever occurs earlier.
  • In the case when VDRV is disabled, the device immediately transitions from power or sleep mode to standby and active modes.