SLVSEQ3B
September 2018 – May 2022
TVS1801
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings - JEDEC
7.3
ESD Ratings - IEC
7.4
Recommended Operating Conditions
7.5
Thermal Information
7.6
Electrical Characteristics
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
8.4.1
Protection Specifications
8.4.2
Reliability Testing
8.4.3
Zero Derating
8.4.4
Bidirectional Operation
8.4.5
Transient Performance
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documenation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRB|8
MPDS118K
Thermal pad, mechanical data (Package|Pins)
DRB|8
QFND058N
Orderable Information
slvseq3b_oa
slvseq3b_pm
7.7
Typical Characteristics
Figure 7-1
8/20-µs Surge Response at 30 A
f = 1 MHz, 30 mVpp, IO to GND
Figure 7-3
Capacitance vs Voltage Bias
Figure 7-5
Breakdown Voltage (1 mA) vs Temperature
Figure 7-2
8/20-µs Surge Clamping Response at 30 A
Figure 7-4
Leakage Current vs Temperature at 18 V
Figure 7-6
Dynamic Leakage vs Signal Slew Rate Across Temperature