SLVSEG2B
September 2018 – September 2022
TVS3301
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings - JEDEC
8.3
ESD Ratings - IEC
8.4
Recommended Operating Conditions
8.5
Thermal Information
8.6
Electrical Characteristics
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.4
Device Functional Modes
9.4.1
Protection Specifications
9.4.2
Reliability Testing
9.4.3
Minimal Derating
9.4.4
Bidirectional Operation
9.4.5
Transient Performance
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
10.2.4
PLC Surge Protection Reference Design
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRB|8
MPDS118K
Thermal pad, mechanical data (Package|Pins)
DRB|8
QFND058N
Orderable Information
slvseg2b_oa
slvseg2b_pm
8.7
Typical Characteristics
Figure 8-1
8/20-µs Surge Response at 27 A
f = 1 MHz, 30 mVpp, IO to GND
Figure 8-3
Capacitance vs Voltage Bias
Figure 8-5
Breakdown Voltage (1 mA) vs Temperature
Figure 8-7
Dynamic Leakage vs Signal Slew Rate Across Temperature
Figure 8-2
8/20-µs Surge Clamping Response at 21 A
Figure 8-4
Leakage Current vs Temperature at 33 V
Figure 8-6
Maximum Surge Current (8/20 µs) vs Temperature