SCES650J April   2006  – October 2020 TXB0104

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: VCCA = 1.2 V
    7. 6.7  Timing Requirements: VCCA = 1.5 V ± 0.1 V
    8. 6.8  Timing Requirements: VCCA = 1.8 V ± 0.15 V
    9. 6.9  Timing Requirements: VCCA = 2.5 V ± 0.2 V
    10. 6.10 Timing Requirements: VCCA = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics: VCCA = 1.2 V
    12. 6.12 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
    13. 6.13 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
    14. 6.14 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
    15. 6.15 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
    16. 6.16 Operating Characteristics: VCCA = 1.2 V to 1.5 V, VCCB = 1.5 V to 1.8 V
    17. 6.17 Operating Characteristics: VCCA = 1.8 V to 3.3 V, VCCB = 1.8 V to 5 V
    18. 6.18 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Input Driver Requirements
      3. 8.3.3 Output Load Considerations
      4. 8.3.4 Enable and Disable
      5. 8.3.5 Pullup or Pulldown Resistors on I/O Lines
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • RUT|12
  • NMN|12
  • YZT|12
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-4D01C876-4C7B-439F-9382-DC2449B11C38-low.gifFigure 5-1 GXU and ZXU Package,12-Pin BGA Microstar Junior(Top View)
GUID-ABA883C7-7A32-49E8-9CB1-7C749C185654-low.gifFigure 5-3 YZT Package,12-Pin DSBGA(Top View)
GUID-457A663E-9996-4A1C-87FD-3EF4DE311363-low.gif
NC − No internal connection
Figure 5-5 RGY Package,14-Pin VQFN With Exposed Thermal Pad(Top View)
GUID-4D01C876-4C7B-439F-9382-DC2449B11C38-low.gifFigure 5-2 NMN Package,12-Pin NFBGA(Top View)
GUID-D2A1EBB5-E985-42EC-A5AA-0960E2A6D917-low.gif
NC − No internal connection
Figure 5-4 D or PW Package,14-Pin SOIC or TSSOP(Top View)
GUID-5479AFA2-7B6B-4F2C-831D-5536B64A55F5-low.gifFigure 5-6 RUT Package,12-Pin UQFN(Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME D, PW RGY RUT GXU, ZXU, NMN YZT
A1 2 2 2 A1 A3 I/O Input/output 1. Referenced to VCCA.
A2 3 3 3 A2 B3 I/O Input/output 2. Referenced to VCCA.
A3 4 4 4 A3 C3 I/O Input/output 3. Referenced to VCCA.
A4 5 5 5 A4 D3 I/O Input/output 4. Referenced to VCCA.
B1 13 13 10 C1 A1 I/O Input/output 1. Referenced to VCCB.
B2 12 12 9 C2 B1 I/O Input/output 2. Referenced to VCCB.
B3 11 11 8 C3 C1 I/O Input/output 3. Referenced to VCCB.
B4 10 10 7 C4 D1 I/O Input/output 4. Referenced to VCCB.
GND 7 7 6 B4 D2 — Ground
NC 6, 9 6,9 — — — — No connection. Not internally connected.
OE 8 8 12 B3 C2 I Tri-state output-mode enable. Pull OE low to place all outputs in tri-state mode. Referenced to VCCA.
VCCA 1 1 1 B2 B2 — A-port supply voltage 1.2 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB.
VCCB 14 14 11 B1 A2 — B-port supply voltage 1.65 V ≤ VCCB ≤ 5.5 V.
Thermal pad — — — — — For the RGY package, the exposed center thermal pad must either be connected to Ground or left electrically open.
Table 5-2 Pin Assignments: NMN, GXU and ZXU Package
A B C
4 A4 GND B4
3 A3 OE B3
2 A2 VCCA B2
1 A1 VCCB B1
Table 5-3 Pin Assignments: YZT Package
3 2 1
D A4 GND B4
C A3 OE B3
B A2 VCCA B2
A A1 VCCB B1