SCES854A May   2014  – September 2017 TXS0102-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements — VCCA = 1.8 V ± 0.15 V
    7. 6.7  Timing Requirements — VCCA = 2.5 V ± 0.2 V
    8. 6.8  Timing Requirements — VCCA = 3.3 V ± 0.3 V
    9. 6.9  Switching Characteristics — VCCA = 1.8 V ± 0.15 V
    10. 6.10 Switching Characteristics — VCCA = 2.5 V ± 0.2 V
    11. 6.11 Switching Characteristics — VCCA = 3.3 V ± 0.3 V
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuits
    2. 7.2 Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Input Driver Requirements
      3. 8.3.3 Power Up
      4. 8.3.4 Enable and Disable
      5. 8.3.5 Pullup and Pulldown Resistors on I/O Lines
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TXS0102-Q1 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The A port is able to accept I/O voltages ranging from 1.65 V to 3.6 V, while the B port can accept I/O voltages from 2.3 V to 5.5 V. The device is a pass gate architecture with edge rate accelerators (one shots) to improve the overall data rate. 10-kΩ pullup resistors, commonly used in open drain applications, have been conveniently integrated so that an external resistor is not needed. While this device is designed for open drain applications, the device can also translate push-pull CMOS logic outputs.

8.2 Functional Block Diagram

TXS0102-Q1 new-functional-block-diagram.png

8.3 Feature Description

8.3.1 Architecture

The TXS0102-Q1 architecture (see Figure 10) does not require a direction-control signal in order to control the direction of data flow from A to B or from B to A.

TXS0102-Q1 architecture_sces854.gif Figure 10. Architecture of a TXS01xx Cell

Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup resistor to VCCB. The output one-shots detect rising edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1, T2) for a short duration which speeds up the low-to-high transition.

8.3.2 Input Driver Requirements

The fall time (tfA, tfB) of a signal depends on the output impedance of the external device driving the data I/Os of the TXS0102-Q1 device. Similarly, the tPHL and maximum data rates also depend on the output impedance of the external driver. The values for tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is less than 50 Ω.

8.3.3 Power Up

During operation, assure that VCCA  ≤ VCCB at all times. During power-up sequencing, VCCA  ≥ VCCB does not damage the device, so any power supply can be ramped up first.

8.3.4 Enable and Disable

The TXS0102-Q1 device has an OE input that disables the device by setting OE low, which places all I/Os in the high-impedance state. The disable time (tdis) indicates the delay between the time when the OE pin goes low and when the outputs actually enter the high-impedance state. The enable time (ten) indicates the amount of time the user must allow for the one-shot circuitry to become operational after the OE pin is taken high.

8.3.5 Pullup and Pulldown Resistors on I/O Lines

Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O to VCCA or VCCB (in parallel with the internal 10-kΩ resistors).

8.4 Device Functional Modes

The TXS0102-Q1 device has two functional modes, enabled and disabled. To disable the device set the OE input low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device.