SCES642L December   2007  – November 2024 TXS0108E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: TA = –40°C to 85°C
    6. 5.6  Timing Requirements: VCCA = 1.5V ± 0.1 V
    7. 5.7  Timing Requirements: VCCA = 1.8V ± 0.15V
    8. 5.8  Timing Requirements: VCCA = 2.5V ± 0.2V
    9. 5.9  Timing Requirements: VCCA = 3.3V ± 0.3V
    10. 5.10 Switching Characteristics: VCCA = 1.5V ± 0.1V
    11. 5.11 Switching Characteristics: VCCA = 1.8V ± 0.15V
    12. 5.12 Switching Characteristics: VCCA = 2.5V ± 0.2V
    13. 5.13 Switching Characteristics: VCCA = 3.3V ± 0.3V
    14. 5.14 Operating Characteristics: VCCA = 1.5V to 3.3V, VCCB = 1.5V to 3.3V
    15. 5.15 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuits
    2. 6.2 Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Architecture
      2. 7.3.2 Input Driver Requirements
      3. 7.3.3 Output Load Considerations
      4. 7.3.4 Enable and Disable
      5. 7.3.5 Pull-up or Pull-down Resistors on I/O Lines
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1.      Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Architecture

Figure 7-1 shows semi-buffered architecture design this application requires for both push-pull and open-drain mode. This application uses edge-rate accelerator circuitry (for both the high-to-low and low-to-high edges), a high-on-resistance N-channel pass-gate transistor (on the order of 300Ω to 500Ω) and pull-up resistors (to provide DC-bias and drive capabilities) to meet these requirements. This design does not need a direction-control signal to control the direction of data flow from A to B or from B to A. The resulting implementation supports both low-speed open-drain operation as well as high-speed push-pull operation.

TXS0108E Architecture of a TXS0108E CellFigure 7-1 Architecture of a TXS0108E Cell

When transmitting data from A-ports to B-ports, during a rising edge the one-shot circuit (OS3) turns on the PMOS transistor (P2) for a short-duration which reduces the low-to-high transition time. Similarly, during a falling edge, when transmitting data from A to B, the one-shot circuit (OS4) turns on the N-channel MOSFET transistor (N2) for a short-duration which speeds up the high-to-low transition. The B-port edge-rate accelerator consists of one-shot circuits OS3 and OS4. Transistors P2 and N2 and serves to rapidly force the B port high or low when a corresponding transition is detected on the A port.

When transmitting data from B- to A-ports, during a rising edge the one-shot circuit (OS1) turns on the PMOS transistor (P1) for a short-duration which reduces the low-to-high transition time. Similarly, during a falling edge, when transmitting data from B to A, the one-shot circuit (OS2) turns on NMOS transistor (N1) for a short-duration and this speeds up the high-to-low transition. The A-port edge-rate accelerator consists of one-shots OS1 and OS2, transistors P1 and N1 components and form the edge-rate accelerator and serves to rapidly force the A port high or low when a corresponding transition is detected on the B port.