SCES930B April   2021  – March 2022 TXU0104-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions—TXU0104-Q1
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Tsk, TMAX
    7. 7.7  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    8. 7.8  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    9. 7.9  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    10. 7.10 Switching Characteristics, VCCA = 2.5 ± 0.2 V
    11. 7.11 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    12. 7.12 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    13. 7.13 Operating Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Load Circuit and Voltage Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 9.3.1.1 Inputs with Integrated Static Pull-Down Resistors
      2. 9.3.2  Control Logic (OE) with VCC(MIN) Circuitry
      3. 9.3.3  Balanced High-Drive CMOS Push-Pull Outputs
      4. 9.3.4  Partial Power Down (Ioff)
      5. 9.3.5  VCC Isolation and VCC Disconnect
      6. 9.3.6  Over-Voltage Tolerant Inputs
      7. 9.3.7  Glitch-Free Power Supply Sequencing
      8. 9.3.8  Negative Clamping Diodes
      9. 9.3.9  Fully Configurable Dual-Rail Design
      10. 9.3.10 Supports High-Speed Translation
      11. 9.3.11 Wettable Flanks
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Regulatory Requirements
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.13 Operating Characteristics

TA = 25℃ (1)
PARAMETERTest ConditionsSupply Voltage (VCCB = VCCA)UNIT
1.2 ± 0.1V1.5 ± 0.1V1.8 ± 0.15V2.5 ± 0.2V3.3 ± 0.3V5.0 ± 0.5V
TYPTYPTYPTYPTYPTYP
CpdA (2)A to B: outputs enabledA Port
CL = 0, RL = Open
f = 10 MHz
trise = tfall = 1 ns		222223pF
A to B: outputs disabled222223
B to A: outputs enabled121212131316
B to A: outputs disabled222223
CpdB (3)A to B: outputs enabledB Port
CL = 0, RL = Open
f = 10 MHz
trise = tfall = 1 ns		121212131316pF
A to B: outputs disabled222223
B to A: outputs enabled222223
B to A: outputs disabled222223
(1) See the CMOS Power Consumption and Cpd Calculation application report for additional information about how power dissipation capacitance affects power consumption.
(2) A-Port power dissipation capacitance per transceiver.
(3) B-Port power dissipation capacitance per transceiver.