SCES935A May   2021  – November 2021 TXU0304

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions—TXU0304
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Tsk, TMAX
    7. 7.7  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    8. 7.8  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    9. 7.9  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    10. 7.10 Switching Characteristics, VCCA = 2.5 ± 0.2 V
    11. 7.11 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    12. 7.12 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    13. 7.13 Operating Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Load Circuit and Voltage Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 9.3.1.1 Inputs with Integrated Static Pull-Down Resistors
      2. 9.3.2  Control Logic (OE) with VCC(MIN) Circuitry
      3. 9.3.3  Balanced High-Drive CMOS Push-Pull Outputs
      4. 9.3.4  Partial Power Down (Ioff)
      5. 9.3.5  VCC Isolation and VCC Disconnect
      6. 9.3.6  Over-Voltage Tolerant Inputs
      7. 9.3.7  Glitch-Free Power Supply Sequencing
      8. 9.3.8  Negative Clamping Diodes
      9. 9.3.9  Fully Configurable Dual-Rail Design
      10. 9.3.10 Supports High-Speed Translation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Regulatory Requirements
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, generators supply all input pulses that have the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • Δt/ΔV ≤ 1 ns/V

GUID-01D829A1-9FC2-4D2D-ABA7-D1C1DB2BE0E6-low.gif
CL includes probe and jig capacitance.
Figure 8-1 Load Circuit
Table 8-1 Load Circuit Conditions
ParameterVCCORLCLS1VTP
tpdPropagation (delay) time1.1 V – 5.5 V10 kΩ5 pFOpenN/A
ten, tdisEnable time, disable time1.1 V – 1.6 V10 kΩ5 pF2 × VCCO0.1 V
1.65 V – 2.7 V10 kΩ5 pF2 × VCCO0.15 V
3.0 V – 5.5 V10 kΩ5 pF2 × VCCO0.3 V
ten, tdisEnable time, disable time1.1 V – 1.6 V10 kΩ5 pFGND0.1 V
1.65 V – 2.7 V10 kΩ5 pFGND0.15 V
3.0 V – 5.5 V10 kΩ5 pFGND0.3 V
GUID-AD952B41-4C95-42F8-A08D-6B3C116D737A-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 8-2 Propagation Delay
GUID-454A7563-88AA-4488-801D-C9EF1F403605-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 8-3 Input Transition Rise and Fall Rate
GUID-9F15F0FC-5FFF-4BD7-9DC4-DCF2C2EC04C3-low.gif
  1. Output waveform on the condition that input is driven to a valid Logic Low.
  2. Output waveform on the condition that input is driven to a valid Logic High.
  3. VCCO is the supply pin associated with the output port.
  4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 8-4 Enable Time And Disable Time