The TXV0106-Q1 not only solves voltage mismatch between interfaces but also solves power sequencing challenges. In some Ethernet applications, you may have a multi-core RGMII system with an Ethernet switch Figure 8-3. In other applications, you may have a standard Ethernet interface with one MAC and PHY. In either case, it is necessary to power up each device properly. This will prevent the I/O pins from powering up before the core blocks, which can cause in-rush current during power up or bus contention and other malfunctions.

Figure 8-3 Multi-Core RGMII Communication

Low Dropout (LDO) devices are a common way to power up devices, but they do not provide any power sequencing features. As can be seen in Figure 8-4, before the 1.8V can be applied to the MAC, the input of the LDO will need to come up first. This will result in the PHY powering up which can lead to in-rush current flowing into the MAC I/O pins.

Figure 8-4 Residual Current Flowing Into MAC I/O Pins After PHY is Powered Up

With the TXV0106-Q1 supporting the I_off-float feature, in-rush current from improper power sequencing can be prevented. When either power supply pin is at 0V or below 100mV, the I/O pins become high impedance until both pins go above 100mV. The high impedance state will prevent any in-rush current from flowing to the opposite side.

Figure 8-5 Using the TXV0106-Q1 for Power Isolation

For additional information on the TXV0106-Q1 and power isolation use cases, see the Solving Power Sequencing Challenges for Ethernet RGMII Communications application note.