SCES958B July   2023  – April 2024 TXV0108-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 1.2 ± 0.06 V
    7. 5.7  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    8. 5.8  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    9. 5.9  Switching Characteristics, VCCA = 3.3 ± 0.3 V
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 VCC Isolation and VCC Disconnect (Ioff-float)
      4. 7.3.4 Over-Voltage Tolerant Inputs
      5. 7.3.5 Negative Clamping Diodes
      6. 7.3.6 Fully Configurable Dual-Rail Design
      7. 7.3.7 Supports Timing Sensitive Translation
      8. 7.3.8 Wettable Flanks
      9. 7.3.9 Integrated Damping Resistor and Impedance Matching
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Solving Power Sequencing Challenges with the TXV0108-Q1
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGY|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Solving Power Sequencing Challenges with the TXV0108-Q1

The TXV0108-Q1 not only solves voltage mismatch between interfaces but also solves power sequencing challenges. As shown in Figure 8-3, a multi-core RGMII system with an Ethernet switch may be present in some Ethernet applications. In other applications, there may be a standard Ethernet interface with one MAC and PHY. In either case, it is necessary to power up each device properly. This will prevent the I/O pins from powering up before the core blocks, which can cause in-rush current during power up or bus contention and other malfunctions.

GUID-20231130-SS0I-2VH0-PMVR-F3QJTGXTPHWS-low.svg Figure 8-3 Multi-Core RGMII Communication
Low Dropout (LDO) devices are a common way to power up devices, but they do not provide any power sequencing features. As shown in Figure 8-4, before the 1.8V can be applied to the MAC, the input of the LDO will need to come up first. This will result in the PHY powering up which can lead to in-rush current flowing into the MAC I/O pins.

GUID-20231130-SS0I-R43D-C9WJ-TPR5PHH73LH4-low.svg Figure 8-4 Residual Current Flowing Into MAC I/O Pins After PHY is Powered Up

With the TXV0108-Q1 supporting the Ioff-float feature, in-rush current from improper power sequencing can be prevented. When either power supply pin is at 0V or below 100mV, the I/O pins become high impedance until both pins go above 100mV. The high impedance state will prevent any in-rush current from flowing to the opposite side.

GUID-20231201-SS0I-2BLL-8WHT-TFHCK5WC7DKJ-low.svg Figure 8-5 Using the TXV0108-Q1 for Power Isolation

For additional information on the TXV0108-Q1 and power isolation use cases, see the Solving Power Sequencing Challenges for Ethernet RGMII Communications application note.