SCES958B July   2023  – April 2024 TXV0108-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 1.2 ± 0.06 V
    7. 5.7  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    8. 5.8  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    9. 5.9  Switching Characteristics, VCCA = 3.3 ± 0.3 V
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 VCC Isolation and VCC Disconnect (Ioff-float)
      4. 7.3.4 Over-Voltage Tolerant Inputs
      5. 7.3.5 Negative Clamping Diodes
      6. 7.3.6 Fully Configurable Dual-Rail Design
      7. 7.3.7 Supports Timing Sensitive Translation
      8. 7.3.8 Wettable Flanks
      9. 7.3.9 Integrated Damping Resistor and Impedance Matching
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Solving Power Sequencing Challenges with the TXV0108-Q1
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGY|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Switching Characteristics, VCCA = 3.3 ± 0.3 V

Minimum and maximum limits apply over the recommended temperature range at CL = 15 pF and 250 Mbps, unless otherwise indicated.
PARAMETER FROM TO B-Port Supply Voltage (VCCB) UNIT
1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
tpd Propagation delay A B 1.2 3.8 1.2 2.7 1.1 2.3 ns
B A 1.2 3.0 1.1 2.5 1.1 2.3
tdis Disable time OE A 2.0 5.5 2.0 5.5 2.0 5.5 ns
B 2.2 6.0 1.8 4.5 2.0 5.5
ten Enable time OE A 1.0 3.0 1.0 3.0 1.0 3.0 ns
B 1.2 4.5 0.95 3.0 0.85 2.7
tSKO Output channel-to-channel skew (1) A B -380 380 -230 230 -170 170 ps
B A -330 330 -190 190 -165 165
TR Rise time (2) A B 0.50 1.3 0.40 1.0 0.35 0.90 ns
B A 0.35 0.80 0.35 0.80 0.35 0.80
TF Fall time (2) A B 0.45 1.3 0.35 1.0 0.35 0.80 ns
B A 0.35 0.80 0.35 0.80 0.35 0.80
Duty Cycle Duty cycle variation A B 46 50 54 48 50 53 48 50 52 %
B A 47 50 54 47 50 53 47 50 52
TR_5pF Rise time (2) (3) A B 0.30 0.80 0.20 0.55 0.15 0.45 ns
B A 0.15 0.45 0.15 0.45 0.15 0.45
TF_5pF Fall time (2) (3) A B 0.25 0.80 0.20 0.60 0.20 0.45 ns
B A 0.15 0.40 0.15 0.45 0.20 0.45
tSKO_5pF Output channel-to-channel skew (1) (3) A B -265 265 -145 145 -140 140 ps
B A -310 310 -170 170 -120 120
Duty Cycle_5pF Duty cycle variation (3) A B 48 50 53 49 50 52 49 50 52 %
B A 48 50 54 48 50 52 48 50 52
tjit(pp) Peark-to-peak jitter (250 Mbps 215- 1 PRBS input) A or B A or B 115 390 75 330 75 330 ps
(1) Skew parameter also includes jitter
(2) Rise and fall time is measured at 20% - 80%
(3) Parameters tested under RGMII input transition (≤ 2 ns/V) rise and fall time. CLOAD = 5 pF