SLVS010 Data sheet | TI.com

SLVS010X january 1976 – june 2023 UA78L

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

D|8
PK|3
LP|3

Thermal pad, mechanical data (Package|Pins)

PK|3
- PPTD070

Orderable Information

6.14 Typical Characteristics

at specified junction temperature T_J = 25 °C, V_I = 10 V, V_O = 5 V, C_IN = 0.33 µF, C_OUT = 0.1µF, and I_O = 1 mA (unless otherwise noted)

Figure 6-1 V_O vs Temperature for New Chip

Figure 6-3 Load Regulation for Legacy Chip

Figure 6-5 Load Regulation for New Chip

I_O = 40 mA

Figure 6-7 Line Regulation at I_O = 40 mA for New Chip at T_J = 25°C

I_O = 40 mA

Figure 6-9 Line Regulation at I_O = 40 mA for New Chip

Figure 6-11 Bias Current vs Load Current for Legacy Chip

Figure 6-13 Bias Current vs Load Current for New Chip

I_O = 40 mA

Figure 6-15 Bias Current vs Input Voltage for New Chip at T_J = 25°C

Figure 6-17 Bias Current vs Input Voltage at I_O = 1 mA for New Chip

V_O = 90% of V_O (typ)

Figure 6-19 I_CL vs Temperature for New Chip

V_I = 23 V, V_O = 15 V

Figure 6-21 Noise Spectral Density vs Frequency and I_O for New Chip

V_I = 23 V, V_O = 15 V

Figure 6-23 PSRR vs Frequency and I_O for New Chip

I_O = 40 mA

Figure 6-2 V_O vs Temperature for New Chip

Figure 6-4 Load Regulation for New Chip at T_J = 25°C

I_O = 40 mA

Figure 6-6 Line Regulation at I_O = 40 mA for Legacy Chip

Figure 6-8 Line Regulation at I_O = 1 mA for New Chip at T_J = 25°C

Figure 6-10 Line Regulation at I_O = 1 mA for New Chip

Figure 6-12 Bias Current vs Load Current for New Chip at T_J = 25°C

I_O = 40 mA

Figure 6-14 Bias Current vs Input Voltage for Legacy Chip

I_O = 40 mA

Figure 6-16 Bias Current vs Input Voltage for New Chip

V_O = 0 V

Figure 6-18 I_SC vs V_I for New Chip

V_I = 9 V, V_O = 3.3 V

Figure 6-20 Noise Spectral Density vs Frequency and I_O for New Chip

V_I = 9 V, V_O = 3.3 V

Figure 6-22 PSRR vs Frequency and I_O for New Chip