SLUSAG0A March   2011  – March 2016 UC1707-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Switching Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Simplified Internal Circuitry
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Shutdown Circuit Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

UC1707-SP was designed specifically as a power MOSFET driver for switching-mode power supply applications. It is capable of providing fast transitions and high-peak current required by power MOSFETs. One of the most important factors while developing the UC1707-SP was to isolate the high speed switching noise from the low level analog signals at the PWM. Separate supply and return paths at the driver signal inputs and power outputs further enhance noise immunity.

8.2 Functional Block Diagram

UC1707-SP bd_lus177.gif

8.3 Feature Description

8.3.1 Shutdown Circuit Description

The function of the circuitry is to be able to provide a shutdown of the device. This is defined as functionality that will drive both outputs to the low state. There are three different inputs that govern this shutdown capability.

  • Analog Stop Pins — The differential inputs to this comparator provide a way to execute a shutdown.
  • Latch Disable Pin — Assuming that the Shutdown pin is left open, a high on this pin disables the latching functionality of the Analog Stop shutdown. A low on this pin enables the latching functionality of the Analog Stop shutdown. If a shutdown occurs through the Analog Stop circuit while Latch Disable is high, then the outputs will go low, but will return to normal operation as soon as the Analog Stop circuit allows it. If a shutdown occurs through the Analog Stop circuit while Latch Disable is low, then the outputs will go low and remain low even if the Analog Stop circuit no longer drives the shutdown. The outputs will remain "latched" low (in shutdown) until the Latch Disable goes high and the Analog Stop circuit allows it to return from shutdown or the VIN voltage is cycled to 0 V and then returned above 5 V.
  • Shutdown Pin — This pin serves two purposes.
    1. It can be used as an output of the Analog Stop circuit.
    2. It can be used as an input to force a shutdown or to force the device out of shutdown. This pin can override both the Analog Stop circuit as well as the Latch Disable Pin. When driving hard logic levels into the Shutdown pin, the Latch Disable functionality will be overridden and the Latch Disable will not function as it does when used in conjunction with the Analog Stop circuit. When the Shutdown pin is high, the outputs will be in the low state (shutdown). When the Shutdown pin is low (hard logic low) the outputs will operate normally, regardless of the state of the Latch Disable pin or the Analog Stop pins.

To use the Shutdown Pin with the Latch Disable functional it is necessary to use either a diode in series with the Shutdown signal or to use an open collector pullup so that the Shutdown pin is not pulled low. This configuration will allow the Latch Disable function to work with the Shutdown pin.

8.4 Device Functional Modes

Table 1. UG1707 Shutdown Truth Table

ANALOG STOP LOGIC SHUTDOWN LATCH DISABLE PREVIOUS STATE OF OUTPUT OUTPUT
X 0 X X Follows Input Logic
X 1 X X Low (Shutdown)
1 Open X X Low (Shutdown)
0 Open 0 Shutdown Latched Shutdown(1)
0 Open 0 Normal Follows Input Logic
0 Open 1 X Follows Input Logic
(1) If the output was previously in Shutdown and Latch Disable was low and stays low, then even if the Analog Stop Logic is changed or the Shutdown pin is open, the outputs will remain in Shutdown.