8.3.1 Leading Edge Blanking

The UC1825A-SP performs fixed frequency pulse width modulation control. The UC1825A-SP outputs are alternately controlled. During every other cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%.

To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator. On the falling edge of the clock, the appropriate output is driven high. The end of the pulse is controlled by the PWM comparator, current limit comparator, or the overcurrent comparator.

Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not require any filtering as result of leading edge blanking.

To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy, an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%. The design equation is shown in Equation 1:

Equation 1.

Values of R less than 2 kΩ must not be used.

Leading edge blanking is also applied to the current limit comparator (see Figure 3). After LEB, if the ILIM pin exceeds the 1-V threshold, the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this reason, some noise filtering may be required on the ILIM pin.

Figure 3. Leading Edge Blanking Operational Waveforms

8.3.2 UVLO, Soft-Start, and Fault Management

Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output follows until closed loop regulation takes over.

Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low, as shown in Figure 4. The soft-start cap is then discharged by a 250-μA current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is less than 1.2 V. At this point the fault latch resets and the chip executes a soft-start.

Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions.

Figure 4. Soft-Start and Fault Waveforms

8.3.3 Active Low Outputs During UVLO

The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate (see Figure 5 and Figure 6).

Figure 5. Output Voltage vs Output Current

Figure 6. Output V And I During UVLO

8.3.4 Control Methods

Figure 7 shows the control methods.

Figure 7. Control Methods

8.3.5 Synchronization

The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor (see Figure 8). Program the free running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width must be greater than 10 ns and less than half the discharge time of the oscillator. Figure 9 shows how to synchronize two ICs, with one as master and one as slave. Figure 10 shows the waveforms in a master and slave configuration.

Figure 8. General Oscillator Synchronization

Figure 9. Two Unit Interface

Figure 10. Operational Waveforms

8.3.6 High Current Outputs

Each totem pole output of the UC1825A-SP can deliver a 2-A peak current into a capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground (PGND) pins help decouple the analog circuitry of the device from the high-power gate drive noise. The use of
3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 25 from each output to both VC and PGND are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive or capacitive load, typical of a MOSFET gate, as shown in Figure 11. Schottky diodes must be used because a low forward voltage drop is required.

Figure 11. Power MOSFET Drive Circuit

8.3.7 Open Loop Test Circuit

This test fixture is useful for exercising many functions of this device family and measuring their specifications (see Figure 12). As with any wideband circuit, careful grounding and bypass procedures must be followed. TI highly recommends using a ground plane.

Figure 12. Open Loop Test Circuit Schematic