SLUSDD4B April   2019  – December 2020 UC1843B-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Reference
      3. 7.3.3 Totem-Pole Output
    4. 7.4 Device Functional Modes
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Transformer
        3. 8.2.2.3 RCD Diode Clamp
        4. 8.2.2.4 Output Diode
        5. 8.2.2.5 Output Filter and Capacitor
        6. 8.2.2.6 Compensation
        7. 8.2.2.7 Sense Resistor and Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Feedback Traces
      2. 10.1.2 Input/Output Capacitors
      3. 10.1.3 Compensation Components
      4. 10.1.4 Traces and Ground Planes
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.3 RCD Diode Clamp

For the UC1843B-SP design a resistor and capacitor are used. The resistor and capacitor is generally a value that is found through testing, but starting values can be obtained. To figure out the resistor and capacitor needed for the RCD clamp, one must first pick how much the node is allowed to overshoot. The equation for finding the voltage of the clamp is Equation 17.

Equation 17. Vclamp=Kclamp×Nps×(Vout+VDiode)

Note that Kclamp is recommended to be 1.5 as this will allow for only around 50% overshoot. Knowing the parasitic inductance of the transformer and how much the snubber voltage is allowed to change over the switching cycle, can allow one to figuring out starting values for the resistor and capacitor using Equation 18 and Equation 19.

Equation 18. Rclamp=Vclamp212×Lleakage×IPriPeak2×VclampVclamp-Nps×(Vout+VDiode)×fosc
Equation 19. Cclamp=VclampΔVclamp×Vclamp×Rclamp×fosc

A starting value of 10% is generally used for ΔVclamp.