SLUSDD4B April   2019  – December 2020 UC1843B-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Reference
      3. 7.3.3 Totem-Pole Output
    4. 7.4 Device Functional Modes
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Transformer
        3. 8.2.2.3 RCD Diode Clamp
        4. 8.2.2.4 Output Diode
        5. 8.2.2.5 Output Filter and Capacitor
        6. 8.2.2.6 Compensation
        7. 8.2.2.7 Sense Resistor and Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Feedback Traces
      2. 10.1.2 Input/Output Capacitors
      3. 10.1.3 Compensation Components
      4. 10.1.4 Traces and Ground Planes
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 UVLO

The UVLO circuit ensures that VCC is adequate to make the UC1843B-SP fully operational before enabling the output stage. Figure 7-4 shows that the UVLO turnon and turnoff thresholds are fixed internally at 8.4 V and 7.6 V, respectively. The 0.6-V hysteresis prevents VCC oscillations during power sequencing.

Figure 7-5 shows supply current requirements. Start-up current is < 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as shown in Figure 7-6. During normal circuit operation, VCC is developed from auxiliary winding, WAux, with D1 and CIN. However, at start-up, CIN must be charged to 8.4 V through RIN. With a start-up current of 1 mA, RIN can be as large as 100 kΩ and still charge CIN when VAC = 90-V RMS (low line). Power dissipation in RIN would then be less than 350 mW even under high line (VAC = 130-V RMS) conditions.

During UVLO, the output driver is in a low state. While it does not exhibit the same saturation characteristics as normal operation, it can easily sink 1 mA, enough to ensure the MOSFET is held off. For efficient operations, an LDO can take the place of RIN and be disabled during the operation of the device.

GUID-3ADBCE8E-CF49-4DEB-B1D4-5A96DA50A5E7-low.gifFigure 7-4 UVLO Turnon and Turnoff Threshold
GUID-758F4788-43BD-4CAB-A4D7-DC3FABB632D2-low.gif
During UVLO, the output driver is biased to sink minor amounts of current.
Figure 7-5 Supply Current Requirements
GUID-20B705CE-3756-4145-B7C0-4320F3C645A3-low.gifFigure 7-6 Providing Power to the UC1843B-SP