SLUS871D January   2009  – December 2016 UC1846-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference
      2. 7.3.2  Oscillator
      3. 7.3.3  Slope Compensation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Current Sense Amplifier
      6. 7.3.6  Current Limit
      7. 7.3.7  Shutdown
      8. 7.3.8  Output Section
      9. 7.3.9  Undervoltage Lockout
      10. 7.3.10 Soft-Start
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 8 V (Minimum VIN)
      2. 7.4.2 Synchronization
      3. 7.4.3 Parallel Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscillator Circuit Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor Selection
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Output Inductor Selection
          4. 8.2.1.2.4 Switching Frequency
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Parallel Operation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Soft-Start and Shutdown/Restart Functions Application
      4. 8.2.4 Open-Loop Test Circuit Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VCC Supply voltage 40 V
Collector supply voltage 40 V
VI Analog input voltage (C/S-, C/S+, E/A+, E/A-, Shutdown) –0.3 VIN V
IO Output current, source or sink 500 mA
Reference output current –30 mA
Sync output current –5 mA
Error amplifier output current –5 mA
Soft-start sink current 50 mA
Oscillator charging current 5 mA
TJ(max) Maximum junction temperature 150 °C
Tlead Lead temperature (soldering, 10 s) 300 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TJ Operating junction temperature –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) UC1846-SP UNIT
J (CDIP) W (CFP) FK (LCCC)
16 PINS 16 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 104.2 105.2 N/A °C/W
RθJC(top) Junction-to-case (top) thermal resistance N/A N/A N/A °C/W
RθJB Junction-to-board thermal resistance 36.6 96.8 N/A °C/W
ψJT Junction-to-top characterization parameter 25.0 24.0 N/A °C/W
ψJB Junction-to-board characterization parameter 27.9 82.6 N/A °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.2 8.5 9.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VIN = 15 V, RT = 10 kΩ, CT = 4.7 nF, TA = TJ = –55°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
Output voltage TJ = 25°C, IO = 1 mA 5.04 5.1 5.16 V
Line regulation VIN = 8 to 40 V 5 20 mV
Load regulation IL = 1 to 10 mA 3 15 mV
Temperature stability Over operating range 0.4 mV/°C
Total output variation Over line, load, and temperature(1) 5 5.2 V
Output noise voltage 10 Hz ≤ ƒ ≤ 10 kHz, TJ = 25°C(1) 100 μV
Long-term stability TJ = 125°C, 1000 hr 5 mV
Short-circuit output current VREF = 0 V –10 –45 mA
OSCILLATOR
Initial accuracy TJ = 25°C 39 43 47 kHz
Voltage stability VIN = 8 to 40 V –1% 2%
Temperature stability Over operating range –1%
Sync output high level 3.9 4.35 V
Sync output low level 2.3 2.5 V
Sync input high level CT = 0 V 3.9 V
Sync input low level CT = 0 V 2.5 V
Sync input current Sync = 3.9 V, CT = 0 V 1.3 1.5 mA
ERROR AMPLIFIER
Input offset voltage 0.5 5 mV
Input bias current –1 –0.6 μA
Input offset current 40 250 nA
Common mode range VIN = 8 to 40 V 0 VIN – 2 V
Open-loop voltage gain ΔVO = 1.2 to 3 V, VCM = 2 V 80 105 dB
Unity-gain bandwidth TJ = 25°C(1) 0.7 1 MHZ
CMRR VCM = 0 to 38 V, VIN = 40 V 75 100 dB
PSRR VIN = 8 to 40 V 80 105 dB
Output sink current VID = –15 mV to –5 V, Comp = 1.2 V 2 6 mA
Output source current VID = 15 mV to 5 V, Comp = 2.5 V –0.5 –0.4 mA
High-level output voltage RL = (Comp) 15 kΩ 4.3 4.6 V
Low-level output voltage RL = (Comp) 15 kΩ 0.7 1 V
CURRENT SENSE AMPLIFIER
Amplifier gain VC/S– = 0 V, C/L SS open(2)(3) 2.5 2.75 3.1 V/V
Maximum differential input signal
(VC/S+ – VC/S–)		 C/L SS open(2), RL (Comp)= 15 kΩ 1.1 1.2 V
Input offset voltage VC/L SS = 0.5 V, Comp open(2) 5 25 mV
CMRR VCM = 1 to 12 V 60 83 dB
PSRR VIN = 8 to 40 V 60 84 dB
Input bias current VC/L SS = 0.5 V, Comp open(2) –10 –2.5 μA
Input offset current VC/L SS = 0.5 V, Comp open(2) 0.08 1 μA
Input common-mode range VIN – 3 V
Delay to outputs TJ = 25°C(1) 200 500 ns
CURRENT LIMIT ADJUST
Current limit offset VC/S– = 0 V, VC/S+ = 0 V, comp open(2) 0.45 0.5 0.55 V
Input bias current VE/A+ = VREF, VE/A– = 0 V –30 –10 μA
SHUTDOWN TERMINAL
Threshold voltage 250 350 400 mV
Input voltage range 0 VIN V
Minimum latching current (IC/S SS)(4)   3 1.5 mA
Maximum non-latching current (IC/S SS)(5)   1.5 0.8 mA
Delay to outputs TJ = 25°C(1) 300 600 ns
OUTPUT
Collector-emitter voltage 40 V
Collector leakage current VC = 40 V 200 μA
Output low-level voltage ISINK = 20 mA 0.1 0.4 V
ISINK = 100 mA 0.4 2.1 V
Output high-level voltage ISOURCE = 20 mA 13 13.5 V
ISOURCE = 100 mA 12 13.5 V
Rise time CL = 1 nF, TJ = 25°C(1) 50 300 ns
Fall time CL = 1 nF, TJ = 25°C(1) 50 300 ns
UVLO
Start-up threshold 7.7 8 V
Threshold hysteresis 0.75 V
TOTAL STANDBY CURRENT
Supply current 17 21 mA
(1) Parameters ensured by design and/or characterization, if not production tested.
(2) Parameter measured at trip point of latch with VE/A+ = VREF, VE/A– = 0 V.
(3) Amplifier gain defined as: G = ΔVComp/ΔVC/S+; VC/S+ = 0 to 1 V.
(4) Current into C/S SS required to latch circuit in shutdown state.
(5) Current into C/S SS assured not to latch circuit in shutdown state.

6.6 Typical Characteristics

UC1846-SP pha_vs_freq_slusbv6.gif
VIN = 20 V TJ = 25°C
Figure 1. Error Amplifier Gain and Phase vs Frequency
UC1846-SP gain_vs_load_slusbv6.gif
.
VIN = 20 V TJ = 25°C
Figure 2. Error Amplifier Open-Loop DC Gain vs Load Resistance