SLUSAQ9B December   2011  – December 2015 UC1875-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLKSYNC
      2. 8.3.2  E/AOUT
      3. 8.3.3  CS+
      4. 8.3.4  FREQSET
      5. 8.3.5  DELSETA-B, DELSETC-D
      6. 8.3.6  EA-
      7. 8.3.7  EA+
      8. 8.3.8  GND
      9. 8.3.9  OUTA - OUTD
      10. 8.3.10 PWRGND
      11. 8.3.11 RAMP
      12. 8.3.12 SLOPE
      13. 8.3.13 SOFTSTART
      14. 8.3.14 VC
      15. 8.3.15 VIN
      16. 8.3.16 VREF
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Lockout Section
      2. 9.1.2 Synchronizing the Oscillator
      3. 9.1.3 Syncing to External TTL/CMOS
      4. 9.1.4 Delay Blocks and Output Stages
      5. 9.1.5 Output Switch Orientation
      6. 9.1.6 Fault/Soft Start
      7. 9.1.7 Slope/Ramp Pins
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Phase-Shifted Fundamentals
        2. 9.2.2.2  Circuit Schematic and Description
        3. 9.2.2.3  Initial Conditions (Time: t = t(0))
        4. 9.2.2.4  Right Leg Resonant Transition Interval (Time: t(0) < t < t(1))
        5. 9.2.2.5  Clamped Freewheeling Interval (Time: t(1) < t < t(2))
        6. 9.2.2.6  Left Leg Transition Interval (Time: t(2) < t < t(3))
        7. 9.2.2.7  Power Transfer Interval (Time: t(3) < t < t(4))
        8. 9.2.2.8  Switch Turn Off (Time: t(4))
        9. 9.2.2.9  Resonant Tank Considerations
        10. 9.2.2.10 Resonant Circuit Limitations
        11. 9.2.2.11 Stored Inductive Energy
        12. 9.2.2.12 Resonant Circuit Summary
        13. 9.2.2.13 Stored Energy Requirements
        14. 9.2.2.14 Minimum Primary Current
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground (GND)
      2. 11.1.2 Bias Supply (VCC)
      3. 11.1.3 Feedback Traces
      4. 11.1.4 Compensation Components
      5. 11.1.5 Traces and Ground Planes
      6. 11.1.6 Current Transformer
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a 10.75-V threshold. 1.5 hysteresis is built in for reliable, boot-strapped chip supply. Overcurrent protection is provided, and will latch the outputs in the OFF state within 70 ns of a fault. The current-fault circuitry implements full-cycle restart operation.

Additional features include an error amplifier with bandwidth in excess of 7 MHz, a 5-V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry.

This device is available in hermetically sealed cerdip, surface mount, and ceramic leadless chip carrier packages for –55°C to 125°C operation.