SLUSAQ9B December   2011  – December 2015 UC1875-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLKSYNC
      2. 8.3.2  E/AOUT
      3. 8.3.3  CS+
      4. 8.3.4  FREQSET
      5. 8.3.5  DELSETA-B, DELSETC-D
      6. 8.3.6  EA-
      7. 8.3.7  EA+
      8. 8.3.8  GND
      9. 8.3.9  OUTA - OUTD
      10. 8.3.10 PWRGND
      11. 8.3.11 RAMP
      12. 8.3.12 SLOPE
      13. 8.3.13 SOFTSTART
      14. 8.3.14 VC
      15. 8.3.15 VIN
      16. 8.3.16 VREF
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Lockout Section
      2. 9.1.2 Synchronizing the Oscillator
      3. 9.1.3 Syncing to External TTL/CMOS
      4. 9.1.4 Delay Blocks and Output Stages
      5. 9.1.5 Output Switch Orientation
      6. 9.1.6 Fault/Soft Start
      7. 9.1.7 Slope/Ramp Pins
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Phase-Shifted Fundamentals
        2. 9.2.2.2  Circuit Schematic and Description
        3. 9.2.2.3  Initial Conditions (Time: t = t(0))
        4. 9.2.2.4  Right Leg Resonant Transition Interval (Time: t(0) < t < t(1))
        5. 9.2.2.5  Clamped Freewheeling Interval (Time: t(1) < t < t(2))
        6. 9.2.2.6  Left Leg Transition Interval (Time: t(2) < t < t(3))
        7. 9.2.2.7  Power Transfer Interval (Time: t(3) < t < t(4))
        8. 9.2.2.8  Switch Turn Off (Time: t(4))
        9. 9.2.2.9  Resonant Tank Considerations
        10. 9.2.2.10 Resonant Circuit Limitations
        11. 9.2.2.11 Stored Inductive Energy
        12. 9.2.2.12 Resonant Circuit Summary
        13. 9.2.2.13 Stored Energy Requirements
        14. 9.2.2.14 Minimum Primary Current
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground (GND)
      2. 11.1.2 Bias Supply (VCC)
      3. 11.1.3 Feedback Traces
      4. 11.1.4 Compensation Components
      5. 11.1.5 Traces and Ground Planes
      6. 11.1.6 Current Transformer
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

Using the conventional full-bridge topology with phase-shifted control technique has already demonstrated its superiority in medium to high power, DC-to-DC power conversion. This control method provides well controlled dv/dt values and zero-voltage switching of all primary side semiconductors in the power stage over nearly all operating conditions. The major benefits offered by this approach are a simpler power stage than its hard switched counterpart, utilizing circuit parasitics instead of being penalized by them, improved efficiency and lower EMI level. These significant advantages are realized with a slightly more complex control algorithm.

The UC1875-SP implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be configured to provide control in either voltage or current-mode operation, with a separate overcurrent shutdown for fast fault protection.

8.2 Functional Block Diagram

UC1875-SP FBD_lusaq9.png

8.3 Feature Description

8.3.1 CLKSYNC

(Bidirectional clock and synchronization pin): Used as an output, this pin provides a clock signal. As an input, this pin provides a synchronization point. In its simplest usage, multiple devices, each with their own local oscillator frequency, may be connected together by the CLOCKSYNC pin and will synchronize on the fastest oscillator. This pin may also be used to synchronize the device to an external clock, provided the external signal is of higher frequency than the local oscillator. A resistor load may be needed on this pin to minimize the clock pulse width.

8.3.2 E/AOUT

(Error Amplifier Output): This is is the gain stage for overall feedback control. Error amplifier output voltage levels below 1 volt will force 0° phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source.

8.3.3 CS+

(Current Sense): The non-inverting input to the current-fault comparator whose reference is set internally to a fixed 2.5 V (separate from VREF). When the voltage at this pin exceeds 2.5 V the current-fault latch is set, the outputs are forced OFF and a SOFT-START cycle is initiated. If a constant voltage above 2.5 V is applied to this pin the outputs are disabled from switching and held in a low state until the CS+ pin is brought below 2.5 V. The outputs may begin switching at 0 degrees phase shift before the SOFTSTART pin begins to rise -- this condition will not prematurely deliver power to the load.

8.3.4 FREQSET

(Oscillator Frequency Set pin): A resistor and a capacitor from FREQSET to GND will set the oscillator frequency.

8.3.5 DELSETA-B, DELSETC-D

(Output Delay Control): The user programmed current flowing from these pins to GND set the turn-on delay for the corresponding output pair. This delay is introduced between turn-off of one switch and turn-on of another in the same leg of the bridge to provide a dead time in which the resonant switching of the external power switches takes place. Separate delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging currents.

8.3.6 EA–

(Error Amplifier Inverting Input): This is normally connected to the voltage divider resistors which sense the power supply output voltage level.

8.3.7 EA+

(Error Amplifier Non-Inverting Input): This is normally connected to a reference voltage used for comparison with the sensed power supply output voltage level at the EA+ pin.

8.3.8 GND

(Signal Ground): All voltages are measured with respect to GND. The timing capacitor, on the FREQSET pin, any bypass capacitor on the VREF pin, bypass capacitors on VIN and the ramp capacitor, on the RAMP pin, should be connected directly to the ground plane near the signal ground pin.

8.3.9 OUTA – OUTD

(Outputs A-D): The outputs are 2 A totem-pole drivers optimized for both MOSFET gates and level-shifting transformers. The outputs operate as pairs with a nominal 50% duty-cycle. The A-B pair is intended to drive one half-bridge in the external power stage and is syncronized with the clock waveform. The C-D pair will drive the other half-bridge with switching phase shifted with respect to the A-B outputs.

8.3.10 PWRGND

(Power Ground): VC should be bypassed with a ceramic capacitor from the VC pin to the section of the ground plane that is connected to PWRGND. Any required bulk reservoir capacitor should parallel this one. Power ground and signal ground may be joined at a single point to optimize noise rejection and minimize DC drops.

8.3.11 RAMP

(Voltage Ramp): This pin is the input to the PWM comparator. Connect a capacitor from here to GND. A voltage ramp is developed at this pin with a slope:

UC1875-SP q_dV_dT_lusaq9.gif

Current mode control may be achieved with a minimum amount of external circuitry, in which case this pin provides slope compensation.

Because of the 1.3 V offset between the ramp input and the PWM comparator, the error amplifier output voltage can not exceed the effective ramp peak voltage and duty cycle clamping is easily achievable with appropriate values of R(SLOPE) and C(RAMP).

8.3.12 SLOPE

(Set Ramp Slope/Slope Compensation): A resistor from this pin to VCC will set the current used to generate the ramp. Connecting this resistor to the DC input line voltage will provide voltage feed-forward.

8.3.13 SOFTSTART

(soft start): SOFTSTART will remain at GND as long as VIN is below the UVLO threshold. SOFTSTART will be pulled up to about 4.8 V by an internal 9 µA current source when VIN becomes valid (assuming a non-fault condition). In the event of a current-fault (CS+ voltage exceeding 2.5 V), SOFTSTART will be pulled to GND and them ramp to 4.8 V. If a fault occurs during the SOFTSTART cycle, the outputs will be immediately disabled and SOFTSTART must charge fully prior to resetting the fault latch.

For paralleled controllers, the SOFTSTART pins may be paralled to a single capacitor, but the charge currents will be additive.

8.3.14 VC

(Output Switch Supply Voltage): This pin supplies power to the output drivers and their associated bias circuitry. Connect VC to a stable source above 3 V for normal operation, above 12 V for best performance. This supply should be bypassed directly to the PWRGND pin with low ESR, low ESL capacitors

8.3.15 VIN

(Primary Chip Supply Voltage): This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12 V for normal operation. To ensure proper chip functionality, these devices will be inactive until VIN exceeds the upper undervoltage lockout threshold. This pin should by bypassed directly to the GND pin with low ESR, low ESL capacitors.

8.3.16 VREF

This pin is an accurate 5 V voltage reference. This output is capable of delivering about 60 mA to peripheral circuitry and is internally short circuit current limited. VREF is disabled while VIN is low enough to force the chip into UVLO. The circuit is also in UVLO until VREF reaches approximately 4.75 V. For best results bypass VREF with a 0.1 µF, low ESR, low ESL, capacitor to the GND pin.

NOTE

When VIN exceeds the UVLO threshold the supply current (IIN) will jump from about 100 µA to a current in excess of 20 µA. If the UC1875-SP is not connected to a well bypassed supply, it may immediately enter UVLO again.

8.4 Device Functional Modes

The UC1875-SP, with its 2-A peak current capability, is prepared for direct drive of the gates or gate-drive transformers of the most commonly used power switches. The UC1875-SP can be configured as a voltage-mode or current-mode controller.

The diagonal bridge switches are driven together in a conventional full-bridge converter, which alternately places the transformer primary across the input supply, VIN, for some period of time, t_ON as shown in Figure 14. Power is only transferred to the output section during the ON times of the switches, which corresponds to a specific duty cycle when operated at a fixed frequency. Additionally, the complete range of required duty cycles is unique to the application, and can be estimated from the power supply input and output voltage specifications.

Rather than driving both of the diagonal full bridge switches together, a deliberate delay can be introduced between their turn-on commands with the phase-shifted approach. This delay is adjusted by the voltage loop of the control circuitry, and essentially results as a phase shift between the two drive signals. The effective duty cycle is controlled by varying the phase shift between the switch drive commands as shown in Figure 12.