UCx52xA Regulating Pulse Width Modulators
- SLUS191D February 1997 – July 2017 UC1525A , UC1527A , UC2525A , UC2527A , UC3525A , UC3527A
  
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DATA SHEET

UCx52xA Regulating Pulse Width Modulators

1 Features

8-V to 35-V Operation
5.1-V Reference Trimmed to 1%
100-Hz to 500-kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Dead-Time Control
Internal Soft Start
Pulse-by-Pulse Shutdown
Input Undervoltage Lockout With Hysteresis
Latching PWM to Prevent Multiple Pulses
Dual Source and Sink Output Drivers

2 Applications

Off-Line and DC/DC Power Supplies
Converters Using Voltage Mode
Single-Ended or Two-Switch Topology Designs
Solar Inverters
Welding Inverters
Motor Control
Battery Chargers

Block Diagram

3 Description

The UC1525A/1527A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip 5.1-V reference is trimmed to 1% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between C_T and the discharge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
UCx52xA	LCCC (20)	8.89 mm × 8.89 mm
	CDIP (16)	19.56 mm × 6.67 mm
	SOIC (16)	10.30 mm × 7.50 mm
	PDIP (16)	19.30 mm × 6.35 mm
	PLCC (20)	8.96 mm × 8.96 mm

For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from C Revision (January 2008) to D Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Added Thermal Information tableGo
Changed R_θJA values in the Thermal Information table: from 80-120 to N/A for J; from 90 to 47.6 for N; from 45-90 to 72.6 for DW; from 43-75 to 55.8 for FN; and from 70-80 to N/A for FK Go
Changed R_θJC values in the Thermal Information table: from 28 to 37.4 (top) and 10.1 (bottom) for J; from 45 to 37.3 (top) for N; from 25 to 34 (top) for DW; from 34 to 33.7 (top) for FN; and from 20 to 32.9 (top) to 3.5 (bottom) for FK Go

5 Pin Configuration and Functions

J and N Package

16-Pin CDIP and PDIP

Top View

UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A Pin_Out_01_SLUS191.gif

FN and FK Packages

20-Pin PLCC or LCCC

Top View

UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A Pin_Out_02_SLUS191.gif

Pin Functions

PIN			I/O	DESCRIPTION
NAME	CDIP, PDIP	PLCC, LCCC	I/O	DESCRIPTION
INV Input	1	2	I	Inverting input to the error amplifier
NI Input	2	3	I	Noninverting input to the error amplifier
SYNC	3	4	I	Oscillator sync terminal
OSC Output	4	5	O	Oscillator frequency output
C_T	5	7	I	Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length.
R_T	6	8	I	Timing resistor connection pin for oscillator frequency programming
Discharge	7	9	I	A single resistor between C_T and the discharge terminals provides dead-time adjustment
Soft Start	8	10	I	Soft-start input pin.
Compensation	9	12	O	Output of the error amplifier for compensation
Shutdown	10	13	I	Pull this pin high to shut down PWM output
Output A	11	14	O	output A of the on-chip drive stage
Ground	12	15	—	Ground return pin
V_C	13	17	—	Power supply pin for the output stage. This pin should be bypassed with a 0.1-µF monolithic ceramic low ESL capacitor with minimal trace lengths.
Output B	14	18	O	Output B of the on-chip drive stage.
+V_IN	15	19	—	Input voltage
V_REF	16	20	O	5.1-V reference. For stability, the reference should be bypassed with a 0.1-µF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane.
NC	—	1, 6, 11, 16	—	No internal connection

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
+V_IN	Supply voltage		40	V
V_C	Collector supply voltage		40	V
	Logic inputs	–0.3	5.5	V
	Analog inputs	–0.3	+V_IN	V
	Output current, source or sink		500	mA
	Reference output current		50	mA
	Oscillator charging current		5	mA
	Power dissipation at T_A = +25°C(2)		1000	mW
	Power dissipation at T_C = +25°C(2)		2000	mW
	Operating junction temperature	–55	150	°C
	Lead temperature (soldering, 10 seconds)		300	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	3000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
+V_IN	Input voltage		8	35	V
V_C	Collector supply voltage		4.5	35	V
	Sink/source load current (steady state)		0	100	mA
	Sink/source load current (peak)		0	400	mA
	Reference load current		0	20	mA
	Oscillator frequency range		100	400	Hz
	Oscillator timing resistor		2	150	kΩ
	Oscillator timing capacitor		0.001	0.01	µF
	Dead time resistor range		0	500	Ω
	Operating ambient temperature	UC1525A, UC1527A	–55	125	°C
		UC2525A, UC2527A	–25	85
		UC3525A, UC3527A	0	70

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCx52xA					UNIT
		FK (LCCC)	J (CDIP)	DW (SOIC)	N (PDIP)	FN (PLCC)
		20 PINS	16 PINS	16 PINS	16 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	N/A	N/A	72.6	47.6	55.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	32.9	37.4	34	37.3	33.7	°C/W
R_θJB	Junction-to-board thermal resistance	32.1	54.2	37.3	27.7	21.1	°C/W
ψ_JT	Junction-to-top characterization parameter	N/A	N/A	8.9	17.3	9.7	°C/W
ψ_JB	Junction-to-board characterization parameter	N/A	N/A	36.8	27.5	20.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.5	10.1	N/A	N/A	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
REFERENCE
Output voltage	T_J = 25°C	UC152xA, UC252xA	5.05	5.1	5.15	V
Output voltage	T_J = 25°C	UC352xA	5	5.1	5.2	V
Line regulation	V_IN = 8 V to 35 V			10	20	mV
Load regulation	I_L = 0 mA to 20 mA			20	50	mV
Temperature stability⁽¹⁾	Over operating			20	50	mV
Total output variation⁽¹⁾	Line, load, and temperature	UC152xA, UC252xA	5		5.2	V
Total output variation⁽¹⁾	Line, load, and temperature	UC352xA	4.95		5.25	V
Shorter circuit current	V_REF = 0, T_J = 25°C			80	100	mA
Output noise Voltage⁽¹⁾	10 Hz ≤ 10 kHz, T_J = 25°C			40	200	µVrms
Long-term stability⁽¹⁾	T_J = 125°C			20	50	mV
OSCILLATOR SECTION⁽²⁾
Initial accuracy⁽¹⁾⁽²⁾	T_J = 25°C			2%	6%
Voltage stability⁽¹⁾⁽²⁾	V_IN = 8 V to 35 V	UC152xA, UC252xA		0.3%	1%
Voltage stability⁽¹⁾⁽²⁾	V_IN = 8 V to 35 V	UC352xA		1%	2%
Temperature stability⁽¹⁾	Over operating			3%	6%
Minimum frequency	R_T = 200 kΩ, C_T = 0.1 mF				120	Hz
Maximum frequency	R_T = 2 kΩ, C_T = 470 pF		400			kHz
Current mirror	I_RT = 2 mA		1.7	2	2.2	mA
Clock amplitude⁽¹⁾⁽²⁾			3	3.5		V
Clock width⁽¹⁾⁽²⁾	T_J = 25°C		0.3	0.5	1	µs
Syncronization threshold⁽¹⁾⁽²⁾			1.2	2	2.8	V
Sync input current	Sync voltage = 3.5 V			1	2.5	mA
ERROR AMPLIFIER SECTION (V_CM = 5.1 V)
Input offset voltage	UC152xA, UC252xA			0.5	5	mV
Input offset voltage	UC352xA			2	10
Input bias current				1	10	µA
Input offset current					1	µA
DC open loop gain	R_L ≥ 10 MΩ		60	75		dB
Gain-bandwidth product⁽¹⁾	A_V = 0 dB, T_J = 25°C		1	2		MHz
DC transconductance⁽¹⁾⁽³⁾	T_J = 25°C, 30 kΩ ≤ R_L ≤ 1 MΩ		1.1	1.5		mS
Low-level output voltage				0.2	0.5	V
High-level output voltage			3.8	5.6		V
Common mode rejection	V_CM = 1.5 V to 5.2 V		60	75		dB
Supply voltage rejection	V_IN = 8 V to 35 V		50	60		dB
PWM COMPARATOR
Minimum duty-cycle					0%
Maximum duty-cycle			45%	49%
Input threshold⁽⁴⁾	Zero duty-cycle		0.7	0.9		V
Input threshold⁽⁴⁾	Maximum duty-cycle			3.3	3.6	V
Input bias current⁽⁴⁾				0.05	1	µA
SHUTDOWN
Soft-start current	V_SD = 0 V, V_SS = 0 V		25	50	80	µA
Soft-start low level	V_SD = 2.5 V			0.4	0.7	V
Shutdown threshold	To outputs, V_SS = 5.1 V, T_J = 25°C		0.6	0.8	1	V
Shutdown input current	V_SD = 2.5 V			0.4	1	mA
Shutdown Delay⁽⁵⁾	V_SD = 2.5 V, T_J = 25°C			0.2	0.5	µS
OUTPUT DRIVERS (EACH OUTPUT) (V_C = 20 V)
Low-level output voltage	I_SINK = 20 mA			0.2	0.4	V
Low-level output voltage	I_SINK = 100 mA			1	2	V
High-level output voltage	I_SOURCE = 20 mA		18	19		V
High-level output voltage	I_SOURCE = 100 mA		17	18		V
Undervoltage lockout	V_COMP and V_SS = High		6	7	8	V
V_C OFF current⁽⁶⁾	V_C = 35 V				200	µA
Rise time⁽⁵⁾	C_L = 1 nF, T_J = 25°C			100	600	ns
Fall time⁽⁵⁾	C_L = 1 nF, T_J = 25°C			50	300	ns
TOTAL STANDBY CURRENT
Supply current	V_IN = 35 V			14	20	mA

(1) These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.

(2) Tested at f_OSC = 40 kHz (R_T = 3.6 kΩ, C_T = 0.01 mF, R_D = 0. Approximate oscillator frequency is defined by UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A Equation1.gif

UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A Equation1.gif

(3) DC transconductance (g_M) relates to DC open-loop voltage gain (A_V) according to the following equation: A_V = gMRL where R_L is the resistance from pin 9 to ground. The minimum g_M specification is used to calculate minimum A_V when the error amplifier output is loaded.

(4) Tested at f_OSC = 40 kHz (R_T = 3.6 kΩ, C_T = 0.01 mF, R_D = 0 Ω.

(5) These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.

(6) Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A.

6.6 Typical Characteristics

UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A D002_SLUS191.gif

Figure 1. Oscillator Charge Time vs R_T and C_T

UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A D004_SLUS191.gif

Figure 3. Maximum Value R_D vs Minimum Value R_T

UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A D003_SLUS191.gif

Figure 2. Oscillator Discharge Time vs R_T C_T

UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A D005_SLUS191.gif

Figure 4. Error Amplifier Voltage Gain and Phase vs Frequency

7 Detailed Description

7.1 Overview

The UCx52xA series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip
5.1-V reference is trimmed to 1% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between CT and the discharge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands.

These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for subnormal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A uses OR logic, which results in a HIGH output level when OFF.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Adjustable Dead-Time Control

A single resistor between CT and the discharge terminals provides a wide range of dead-time adjustment.

7.3.2 Soft Start

Soft start is achieved by connecting the soft-start pin to ground through a capacitor, charged by the 50-µA current source. See Functional Block Diagram.

7.3.3 Input Undervoltage Lockout With Hysteresis

The undervoltage lockout keeps the outputs off and the soft-start capacitor discharged for subnormal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation.

7.3.4 Shutdown and Pulse-by-Pulse Current Limiting

See Shutdown Options (See ).

7.4 Device Functional Modes

This device has no functional modes.

7.4.1 Shutdown Options (See Functional Block Diagram)

Since both the compensation and soft-start terminals have current source pullups, either can readily accept a pull-down signal which only has to sink a maximum of 100 A to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins.

An alternate approach is the use of the shutdown circuitry of the shutdown pin which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on the shutdown pin performs two functions; the PWM latch is immediately set providing the fastest turn-off signal to the outputs; and a 150-A current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding the shutdown pin high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turnon upon release.

The shutdown pin should not be left floating as noise pickup could conceivably interrupt normal operation. All transitions of the voltage on the shutdown pin should be within the time frame of one clock cycle and not repeated at a frequency higher than 10 clock cycles.