SLUS557G March   2003  – December 2016 UC28023 , UC28025

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Control Methods and Test Circuits
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Error Amplifier
      2. 8.3.2 Synchronization
      3. 8.3.3 Constant Volt-Second Clamp Circuit
      4. 8.3.4 Outputs
      5. 8.3.5 Open-Loop Laboratory Test Fixture
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Timing Resistor and Capacitor Selection
        2. 9.2.2.2 Turns Ratio Selection
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Rectifier Diode Selection
        5. 9.2.2.5 Snubber Components Selection
        6. 9.2.2.6 VCC and VC Capacitor Selection
        7. 9.2.2.7 Output Capacitor Selection
        8. 9.2.2.8 Input Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

UC28023 DW or N Packages
16-Pin SOIC or PDIP
Top View
UC28025 DW or N Packages
16-Pin SOIC or PDIP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME UC28023 UC28025
CLOCK 4 4 O Output of the internal oscillator
CT 6 6 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor must be connected to the device ground using minimal trace length.
EAOUT 3 3 O Output of the error amplifier for compensation
GND 10 10 — Analog ground return pin.
ILIM/REF 11 — I Pin to set the current limit threshold externally.
ILIM/SD 9 9 I Input to the current limit comparator and the shutdown comparator.
INV 1 1 I Inverting input to the error amplifier
NI 2 2 I Noninverting input to the error amplifier
OUT 14 — O High current totem pole output of the on-chip drive stage.
OUTA — 11 O High current totem pole output A of the on-chip drive stage.
OUTB — 14 O High current totem pole output B of the on-chip drive stage
PGND 12 12 — Ground return pin for the output driver stage
RAMP 7 7 I Noninverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation this serves as the input voltage feedforward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input.
RT 5 5 I Timing resistor connection pin for oscillator frequency programming
SS 8 8 I Soft-start input pin.
VC 13 13 — Power supply pin for the output stage. This pin must be bypassed with a 0.1-µF monolithic ceramic low ESL capacitor with minimal trace lengths.
VCC 15 15 — Power supply pin for the device. This pin must be bypassed with a 0.1-µF monolithic ceramic low ESL capacitor with minimal trace lengths
VREF 16 16 O 5.1-V reference. For stability, the reference must be bypassed with a 0.1-µF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane.