SLUS191D February   1997  – July 2017 UC1525A , UC1527A , UC2525A , UC2527A , UC3525A , UC3527A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Dead-Time Control
      2. 7.3.2 Soft Start
      3. 7.3.3 Input Undervoltage Lockout With Hysteresis
      4. 7.3.4 Shutdown and Pulse-by-Pulse Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Options (See )
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Theory of Operation
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Timing Resistor and Capacitor Selection
        2. 8.2.3.2 Turns Ratio Selection
        3. 8.2.3.3 Inductor Selection
        4. 8.2.3.4 Rectification Diode Selection
        5. 8.2.3.5 VC Capacitor Selection
        6. 8.2.3.6 Output Capacitor Selection
        7. 8.2.3.7 Input Capacitor Selection
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

J and N Package
16-Pin CDIP and PDIP
Top View
UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A Pin_Out_01_SLUS191.gif
FN and FK Packages
20-Pin PLCC or LCCC
Top View
UC1525A UC1527A UC2525A UC2527A UC3525A UC3527A Pin_Out_02_SLUS191.gif

Pin Functions

PIN I/O DESCRIPTION
NAME CDIP,
PDIP		 PLCC,
LCCC
INV Input 1 2 I Inverting input to the error amplifier
NI Input 2 3 I Noninverting input to the error amplifier
SYNC 3 4 I Oscillator sync terminal
OSC Output 4 5 O Oscillator frequency output
CT 5 7 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length.
RT 6 8 I Timing resistor connection pin for oscillator frequency programming
Discharge 7 9 I A single resistor between CT and the discharge terminals provides dead-time adjustment
Soft Start 8 10 I Soft-start input pin.
Compensation 9 12 O Output of the error amplifier for compensation
Shutdown 10 13 I Pull this pin high to shut down PWM output
Output A 11 14 O output A of the on-chip drive stage
Ground 12 15 — Ground return pin
VC 13 17 — Power supply pin for the output stage. This pin should be bypassed with a
0.1-µF monolithic ceramic low ESL capacitor with minimal trace lengths.
Output B 14 18 O Output B of the on-chip drive stage.
+VIN 15 19 — Input voltage
VREF 16 20 O 5.1-V reference. For stability, the reference should be bypassed with a 0.1-µF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane.
NC — 1, 6, 11, 16 — No internal connection