SLUSF11C February   2023  – March 2024 UCC14341-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Insulation Specifications
    6. 6.6  Electrical Characteristics
    7. 6.7  Safety Limiting Values
    8. 6.8  Safety-Related Certifications
    9. 6.9  Insulation Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Undervoltage Protection
        4. 7.3.4.4 Output Overvoltage Protection
        5. 7.3.4.5 Overpower Protection
        6. 7.3.4.6 Over-Temperature Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 Single RLIM Resistor Selection
        3. 8.2.2.3 RDR Circuit Component Selection
        4. 8.2.2.4 Feedback Resistors Selection
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1.2 COM-VEE Voltage Regulation

COM-VEE output takes VDD-VEE output as the input and creates a regulated output voltage. Considered as an LDO output from VDD-VEE, though the operation principle is not quite the same. Given the input voltage is VDD-VEE, the maximum output voltage from COM to VEE is the voltage between VDD and VEE.

The COM-VEE output regulator stage uses the internal high-side or low-side FETs in series with the external current-limit resistor (RLIM) to charge or discharge the COM-VEE output voltage. The hysteresis control is used to control the switching instance of the two FETs, to achieve an accurately regulated COM-VEE voltage. As shown in Figure 7-2, the COM-VEE output voltage is sensed through the voltage divider RFBVEE_TOP and RFBVEE_BOT on FBVEE pin. TI recommends a 330pF capacitor on FBVEE pin to filter out the switching frequency noise. When the voltage on FBVEE is below the charging threshold, 20mV below the VFBVEE_REF, the charging resistor is kept on and discharging resistor is kept off. COM-VEE output voltage rises. After FBVEE voltage reaches the stop charging threshold, 20mV above the VFBVEE_REF, the charging resistor is turned off. Output voltage rise stops. When the charging resistor is turned off, the discharge resistor is controlled by another hysteresis controller, based on FBVEE pin voltage, with the same reference voltage VFBVEE_REF, and 20mV of hysteresis.

The COM-VEE output regulator stage protects from having the high-side FET stay ON for a long time during a COM to VEE short. This protection feature is implemented by monitoring the RLIM-pin voltage and controlling the high-side FET duty-ratio. When the COM pin voltage is lower than 0.645V while the FBVEE voltage is below 2.48V, the hysteretic control of the COM-VEE regulator is overridden by an approximately 20% duty-ratio control on high-side FET, with a typical on-time of tRLIM_SHORT_CHRG_ ON_TIME and off-time of tRLIM_SHORT_CHRG_ OFF_TIME in each duty cycle. When the COM pin voltage is higher than VRLIM_SHORT_CHRG_CMP_RISE, the duty ratio control is disabled and the hysteretic control resumes to normal operation.

GUID-C2E4C3DE-7559-484B-A720-45BCBC7F6034-low.svgFigure 7-2 COM-VEE Voltage Regulation
GUID-2A88DFB8-DDE2-4E95-81A5-07FD2302B498-low.svgFigure 7-3 COM-VEE Voltage Regulation Diagram