SLUSCK0G November   2017  – November 2024 UCC21220 , UCC21220A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Thermal Derating Curves
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21220 and UCC21220A
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimating Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Revision History

Changes from Revision F (February 2024) to Revision G (November 2024)

  • Updated Features section to reflect device characteristicsGo
  • Changed CMTI from greater than 100V/ns to greater than 125V/nsGo
  • Changed maximum propagation delay from 40ns to typical 33nsGo
  • Deleted bullet on maximum delay matchingGo
  • Changed maximum pulse-width distortion from 5.5ns to 5nsGo
  • Changed maximum VDD power-up delay from 35us to 10usGo
  • Changed maximum VDD output drive supply from 18V to 25VGo
  • Changed operating temperature range to junction temperature rangeGo
  • Deleted bullet on rejecting input pulse shorter than 5nsGo
  • Updated certification to the latest standardsGo
  • Changed CMTI from greater than 100V/ns to greater than 125V/nsGo
  • Deleted sentences on input rejecting short transients and input/output withstanding voltage spikesGo
  • Changed active pull-down from 2.1V max to 2V maxGo
  • Changed 5V UVLO recommended VDD supply minimum from 6V to 6.5VGo
  • Changed DIS pin description; leaving DIS pin open would disable the deviceGo
  • Changed VDDA-VSSA and VDDB-VSSB absmax from 20V to 30VGo
  • Changed all -0.5V minimum to -0.3V to keep consistent with newly released datasheetsGo
  • Changed all absolute maximum value from supply+0.5V to supply+0.3V to keep consistent with newly released datasheetsGo
  • Deleted input signal voltage transient specGo
  • Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
  • Changed VDDA-VSSA and VDDB-VSSB recommended max from 18V to 25VGo
  • Changed 5V-UVLO recommended minimum VDDA/B voltage from 6V to 6.5VGo
  • Deleted ambient temperature specGo
  • Changed junction temperature max from 130°C to 150°CGo
  • Updated thermal values from RθJA = 68.5°C/W, RθJC(top) = 30.5°C/W, RθJB = 22.8°C/W, ψJT = 17.1°C/W, ψJB = 22.5°C/W to RθJA = 80.2°C/W, RθJC(top) = 36.6°C/W, RθJB = 45°C/W, ψJT = 28°C/W, ψJB = 44.3°C/WGo
  • Updated values from PD = 1825mW, PDI = 15mW, PDA/PDB = 905mW to PD = 950mW, PDI = 50mW, PDA/PDB = 450mW. Changed test conditions. Go
  • Updated DIN EN IEC to the latest standard, updated insulation voltage valuesGo
  • Updated barrier capacitance valueGo
  • Deleted safety-related certifications section, certification ongoingGo
  • Changed IS testing condition. Changed IS value from 75mA (with VDDA/B=12V) to 50mA (with VDDA/B=15V) and 30mA (with VDDA/B=25V). Go
  • Updated safety-limiting values from PS = 15mW/905mW/905mW/1825mW to PS = 50mW/750mW/750mW/1550mW Go
  • Updated IVCCI quiescent current spec Typ value from 1.5mA to 1.4mAGo
  • Updated IVDDA/IVDDB quiescent current spec Typ from 1.0mA to 1.2mA and Max value from 1.8mA to 2.0mAGo
  • Updated IVCCI operating current Typ value from 2.5mA to 2.7mA and added Max value 3.2mAGo
  • Updated IVDDA/IVDDB operating current Typ value from 2.5mA to 2.7mA and added Max value 4.4mA. Deleted Cload from test condition. Go
  • Updated values from Rising threshold Min = 5.0V, Typ = 5.5V, Max = 5.9V to Min = 5.7V, Typ = 6.0V, Max = 6.3V Go
  • Updated values from Falling threshold Min = 4.7V, Typ = 5.2V, Max = 5.6V to Min = 5.4V, Typ = 5.7V, Max = 6.0V Go
  • Updated values from Rising threshold Min = 8V, Typ = 8.5V, Max = 9V to Min = 7.7V, Typ = 8.5V, Max = 8.9V Go
  • Updated values from Falling threshold Min = 7.5V, Typ = 8V, Max = 8.5V to Min = 7.2V, Typ = 7.9V, Max = 8.4V Go
  • Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
  • Updated Input high threshold Typ = 1.8V, Max = 2V to Typ = 2V, Max = 2.3V. Deleted Min specGo
  • Deleted Input low threshold voltage Max specGo
  • Updated Input threshold hysteresis Typ = 0.8V to Typ = 1VGo
  • Updated peak current test condition to 0.22uF load capacitance. Changed peak output source current directionGo
  • Updated output resistance test condition from ±10mA to ±5mAGo
  • Deleted output voltage at high/low state specsGo
  • Updated active pull-down Typ = 1.75V, Max = 2.1V to Typ = 1.6V, Max = 2VGo
  • Changed output rise time Typ from 5ns to 8ns. Deleted Max valueGo
  • Changed output fall time Typ from 6ns to 8ns. Deleted Max valueGo
  • Changed minimum pulse width from Typ = 10ns, Max = 20ns to Min = 4ns, Typ = 12ns, Max = 30nsGo
  • Changed propagation delay TPDHL and TPDLH from Typ=28ns, Max = 40ns to Min = 26ns, Typ = 33ns, Max = 45nsGo
  • Changed pulse width distortion max from 5.5ns to 5nsGo
  • Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
  • Changed VCCI power-up delay from Typ = 40us, Max = 59us to Min = 18us, Typ = 42us, Max = 80usGo
  • Deleted VDD power up delay Typ 22us and changed Max from 35us to 10usGo
  • Updated CMTI from Min = 100V/ns to 125V/nsGo
  • Updated thermal curves to match updated characteristicsGo
  • Updated typical char plots to show device characteristics Go
  • Deleted language on deglitch filter. Changed minimum pulse width from typical 10ns to 12nsGo
  • Updated UVLO delay to match new specsGo
  • Updated functional block diagram to reflect device characteristicsGo
  • Changed logic table; leaving DIS pin open disables the driverGo
  • Updated input stage section to match new specsGo
  • Added paragraph on minimum pulse width to Output Stage sectionGo
  • Updated ESD structure diagram to reflect device characteristicsGo
  • Updated device operation mode when DIS is floating. Added recommendation of bypass capacitorGo
  • Changed maximum VDDA/VDDB from 18V to 25VGo

Changes from Revision E (May 2019) to Revision F (February 2024)

  • Changed CTI and Material Group values in insulation specifications and added table noteGo

Changes from Revision D (December 2018) to Revision E (May 2019)

  • Changed Features, Applications, and Description sections Go
  • Changed from Functional Diagram to Typical Application Go
  • Added maximum VCCI Power-up Delay Time: UVLO Rise to OUTA, OUTBGo
  • Added maximum VDDA, VDDB Power-up Delay Time: UVLO Rise to OUTA, OUTB Go

Changes from Revision C (August 2018) to Revision D (December 2018)

  • Changed the marketing status of the UCC21220A from Product Preview to initial release.Go