SLUSCK0G November   2017  – November 2024 UCC21220 , UCC21220A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Thermal Derating Curves
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21220 and UCC21220A
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimating Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
CLR External clearance(1) Shortest pin-to-pin distance through air > 4 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface > 4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 400 V
Material group II
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150 VRMS I-IV
Rated mains voltage ≤ 300 VRMS I-III
Rated mains voltage ≤ 600 VRMS I-II
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1200(6) VPK
VIOWM Maximum working isolation voltage AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test; 850(6) VRMS
DC Voltage 1200(6) VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 × VIOTM, t = 1 s (100% production)		 4242 VPK
VIMP Maximum inpulse voltage Tested in air, 1.2/50-µs waveform per IEC 62368-1 5000 VPK
VIOSM Maximum surge isolation voltage(3) VIOSM ≥ 1.3 x VIMP ; Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-1 6500 VPK
qpd Apparent charge(4) Method a, After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s		 <5 pC
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s		 <5
Method b1; At routine test (100% production) and preconditioning (type test)
Vini = 1.2 × VIOTM; tini = 1 s;
Vpd(m) = 1.5 × VIORM , tm = 1 s		 <5
CIO Barrier capacitance, input to output(5) VIO = 0.4 sin (2πft), f =1 MHz ~1.2 pF
RIO Isolation resistance, input to output(5) VIO = 500 V at TA = 25°C > 1012 Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS =150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 3000 VRMS, t = 60 s. (qualification),
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100% production)		 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
(6) System isolation working voltages need to be verified according to application parameters.