SLUSDU7A March 2020 – August 2024 UCC21320-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Figure 10-1 shows a 2-layer PCB layout example with the signals and key components labeled.
Figure 10-2 and Figure 10-3 shows top and bottom layer traces and copper.
There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling. Figure 10-4 shows a 3D view of the bottom side recommended layout, showing the board cutout.
The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.