SLUSDU7A March   2020  – August 2024 UCC21320-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Disable Response Time
    4. 6.4 Programable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21320 -Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

Equation 19. UCC21320-Q1

where

  • QG: Gate charge of the power transistor.
  • IVDD: The channel self-current consumption with no load at 100kHz.

Therefore, the absolute minimum CBoot requirement is:

Equation 20. UCC21320-Q1

where

  • ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.

In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

Equation 21. UCC21320-Q1

Care should be taken when selecting the bootstrap capacitor to ensure that the VDD to VSS voltage does not drop below the recommended minimum operating level listed in section 6.3. The value of the bootstrap capacitor should be sized such that it can supply the initial charge to switch the power device, and then continuously supply the gate driver quiescent current for the duration of the high-side on-time.

If the supply voltage drops below the UVLO falling threshold because Cboot is too small, the driver will turn off. Unexpected switching of power devices can cause high di/dt and high dv/dt noise on the output of the driver may result in permanent damage to the device.

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor placed very close to VDDx - VSSx pins with a low ESL/ESR. In this example a 100 nF, X7R ceramic capacitor, is placed in parallel with CBoot to optimize the transient performance.

Note:

Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during initial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.