SLUSDU7A March   2020  – August 2024 UCC21320-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Disable Response Time
    4. 6.4 Programable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21320 -Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Revision History

Changes from Revision * (March 2020) to Revision A (August 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Deleted HBM and CDM ESD classification levels from FeaturesGo
  • Changed typical propagation delay from 19ns to 33nsGo
  • Changed minimum pulse width from 10ns to 20nsGo
  • Deleted bullet on 5-ns maximum delay matchingGo
  • Changed CMTI from greater than 100V/ns to greater than 125V/nsGo
  • Deleted surge immunity bulletGo
  • Deleted bullet on >40 years isolation barrierGo
  • Deleted bullet on rejecting shorter than 5ns input pulsesGo
  • Changed operating temperature to new range of junction temperatureGo
  • Deleted sentence on best-in-class propagation delay and PWDGo
  • Changed minimum 100V/ns CMTI to 125V/nsGo
  • Changed capacitor size on DT pin and recommended DT conditionGo
  • Changed channel to channel isolation voltage from 1500V to 1850V for DWK packageGo
  • Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
  • Deleted ambient temperature specGo
  • Changed Max junction temp to 150CGo
  • Updated values from RθJA = 67.3°C/W, RθJC(top) = 34.4°C/W, RθJB = 32.1°C/W, ψJT = 18.0°C/W, ψJB = 31.6°C/W to RθJA = 74.1°C/W, RθJC(top) = 34.1°C/W, RθJB = 32.8°C/W, ψJT = 23.7°C/W, ψJB = 32.1°C/WGo
  • Updated values from PD = 1.05W, PDI = 0.05W, PDA/PDB = 0.5W to PD = 950mW, PDI = 50mW, PDA/PDB = 450mW, Changed test conditions.Go
  • Updated values from DTI = >21mm, VIOSM = 6250VPK to DTI = >17mm, VIOSM = 6500VPK and added VIMP = 5000VPKGo
  • Deleted safety related certifications sectionGo
  • Updated values from IS = 75mA/36mA, PS = 50mW/900mW/900mW/1850mW to IS = 53mA/32mA, PS = 50mW/800mW/800mW/1650mW. Changed first row test condition from VDDA/B=12V to VDDA/B=15VGo
  • Update test condition from VDDA=VDDB=12V to VDDA=VDDB=15VGo
  • Updated VCCI quiescent current typical value from 1.5mA to 1.4mAGo
  • Updated IVDDA/IVDDB quiescent current spec Max value from 1.8mA to 2.5mAGo
  • Updated IVCCI operating current Typ value from 2.0mA to 3.0mA and added Max value 3.5mAGo
  • Added IVDDA/IVDDB operating current Max = 4.2mAGo
  • Updated values from Rising threshold Min = 8.3V, Typ = 8.7V, Max = 9.2V to Min = 7.7V, Typ = 8.5V, Max = 8.9V Go
  • Updated values from Falling threshold Min = 7.8V, Typ = 8.2V, Max = 8.7V to Min = 7.2V, Typ = 7.9V, Max = 8.4V Go
  • Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
  • Updated Input high threshold Min value from 1.6V to 1.2VGo
  • Changed output voltage test condition from VDD=12V to VDD=15V. Changed typical value from 11.95V to 14.95V. Go
  • Updated Deadtime parameter by moving to new Timing Requirements table and added more parametersGo
  • Changed propagation delay TPDHL and TPDLH from Typ = 19ns, Max = 30ns to Typ = 33ns, Max = 45ns and adding Min = 26nsGo
  • Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
  • Added VCCI power up delay Go
  • Updated VDDA/VDDB power-up delay from Max = 100us to 10us Go
  • Updated CMTI from Min = 100V/ns to 125V/nsGo
  • Updated thermal and isolation curves to match updated characteristicsGo
  • Changed test condition from VDDA=VDDB=12V to VDDA=VDDB=15VGo
  • Updated typical characteristics figuresGo
  • Changed delay time for VCCI UVLO and VDD UVLOGo
  • Updated block diagram to include deglitch filter block on driversGo
  • Added paragraph regarding narrow pulseGo
  • Updated ESD diode structureGo
  • Changed recommended DT size from >=2.2nF to <=1nFGo
  • Updated typical schematic DT pin capacitor recommendation Go
  • Changed recommended DT capacitor size to <=1nF Go