SLUSF86 May 2024 UCC21331-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The UCC21331-Q1 has an internal undervoltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the affected output low, regardless of the status of the input pins (INA and INB).
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 7-1). In this condition, the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically around 1.5 V, when no bias power is available.
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is bound to happen when the device starts switching and operating current consumption increases suddenly.
The input side of the UCC21331-Q1 also has an internal undervoltage lock out (UVLO) protection feature. The device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And a signal will cease to be delivered when that pin receives a voltage less than VVCCI_OFF. And, just like the UVLO for VDD, there is hysteresis (VVCCI_HYS) to ensure stable operation.
All versions of the UCC21331-Q1 can withstand an absolute maximum of 30 V for VDD, and 5.5 V for VCCI.
CONDITION | INPUTS | OUTPUTS | ||
---|---|---|---|---|
INA | INB | OUTA | OUTB | |
VCCI-GND < VVCCI_ON during device start up | H | L | L | L |
VCCI-GND < VVCCI_ON during device start up | L | H | L | L |
VCCI-GND < VVCCI_ON during device start up | H | H | L | L |
VCCI-GND < VVCCI_ON during device start up | L | L | L | L |
VCCI-GND < VVCCI_OFF after device start up | H | L | L | L |
VCCI-GND < VVCCI_OFF after device start up | L | H | L | L |
VCCI-GND < VVCCI_OFF after device start up | H | H | L | L |
VCCI-GND < VVCCI_OFF after device start up | L | L | L | L |
CONDITION | INPUTS | OUTPUTS | ||
---|---|---|---|---|
INA | INB | OUTA | OUTB | |
VDD-VSS < VVDD_ON during device start up | H | L | L | L |
VDD-VSS < VVDD_ON during device start up | L | H | L | L |
VDD-VSS < VVDD_ON during device start up | H | H | L | L |
VDD-VSS < VVDD_ON during device start up | L | L | L | L |
VDD-VSS < VVDD_OFF after device start up | H | L | L | L |
VDD-VSS < VVDD_OFF after device start up | L | H | L | L |
VDD-VSS < VVDD_OFF after device start up | H | H | L | L |
VDD-VSS < VVDD_OFF after device start up | L | L | L | L |