SLUSF86 May 2024 UCC21331-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENTS | ||||||
IVCC | VCC quiescent current | VINx = 0 V, EN = VCC; VCC=3.3V | 1.4 | 2 | mA | |
VINx = 0 V, EN = VCC; VCC=5V | 1.4 | 2 | ||||
VINx = VCC, EN = VCC; VCC=3.3V | 4.2 | 4.8 | ||||
VINx = VCC, EN = VCC; VCC=5V | 4.2 | 4.8 | ||||
VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; VCC=3.3V | 2.7 | 3.2 | ||||
VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; VCC=5V | 2.7 | 3.2 | ||||
IVDDx | VDDx quiescent current | VINx = 0 V, EN = VCC; | 1.2 | 2 | mA | |
VINx = 0 V, EN = VCC; VDD=25V | 1.4 | 2.3 | ||||
VINx = VCC, EN = VCC; | 1.4 | 2.2 | ||||
VINx = VCC, EN = VCC; VDD=25V | 1.5 | 2.5 | ||||
VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; | 2.7 | 4.4 | ||||
VINx PWM at 0V to VCC at fSW = 500kHz, EN = VCC; VDD=25V | 2.7 | 4.4 | ||||
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS | ||||||
VVCC_ON | VCC UVLO Rising Threshold | 2.55 | 2.7 | 2.85 | V | |
VVCC_OFF | VCC UVLO Falling Threshold | 2.35 | 2.5 | 2.65 | ||
VVCC_HYS | VCC UVLO Threshold Hysteresis | 0.2 | ||||
tVCC+ to OUT | VCC UVLO ON Delay | 18 | 42 | 80 | µs | |
tVCC– to OUT | VCC UVLO OFF Delay | 0.5 | 1.2 | 7 | ||
tVCCFIL | VCC UVLO Deglitch Filter | 0.4 | 0.9 | 3.1 | ||
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS AND DELAY | ||||||
VVDD_ON | VDDx UVLO Rising Threshold | 12-V UVLO Option (Metal Option) | 11.7 | 12.5 | 13.3 | V |
VVDD_OFF | VDDx UVLO Falling Threshold | 10.7 | 11.5 | 12.3 | ||
VVDD_HYS | VDDx UVLO Threshold Hysteresis | 1.0 | ||||
tVDD+ to OUT | VDDx UVLO ON Delay | 10 | µs | |||
tVDD– to OUT | VDDx UVLO OFF Delay | 0.1 | 0.5 | 2 | ||
tVDDFIL | VDDx UVLO Deglitch Filter | 0.1 | 0.17 | |||
INA, INB, AND EN/ | ||||||
VINxH, VENH | Input High Threshold Voltage | 2 | 2.3 | V | ||
VINxL, VENH | Input Low Threshold Voltage | 0.8 | 1 | |||
VINx_HYS, , VEN_HYS |
Input Threshold Hysteresis | 1 | ||||
RINxD | INx Pin Pull Down Resistance | INx = 3.3V | 50 | 90 | 185 | kΩ |
RENU | EN Pin Pull Down Resistance | EN = 3.3V | 50 | 90 | 185 | kΩ |
OUTPUT DRIVER STAGE | ||||||
IO+ | Peak Output Source Current | CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz | –4 | A | ||
IO– | Peak Output Sink Current | CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz | 6 | A | ||
ROH | Pull up resistance | IOUTx = –0.05A | 5 | Ω | ||
ROL | Pull down resistance | IOUTx = 0.05A | 0.55 | |||
ACTIVE PULL-DOWN | ||||||
VOUTPD | Output Active Pull Down on OUTx | IOUT = 200mA, VDDx floating and unpowered. | 1.6 | 2 | V | |
VOUTPD | Output Active Pull Down on OUTx | IOUT = 200mA, CVDD=100nF and unpowered. | 1.6 | 2 | V | |
DEADTIME AND OVERLAP PROGRAMMING | ||||||
DTS | Disable DT Function | DT pin open or pull DT pin to VCC | Output overlapping determined by INA, INB | - | ||
Deadtime Programming for RDT≤0.15kΩ | RDT=0~0.15kΩ | -6 | 0.2 | 6 | ns | |
Deadtime Programming for 1.7kΩ≤RDT≤100kΩ DT (ns) = 8.6×RDT(kΩ) + 13 |
RDT = 10 kΩ | 86 | 99 | 112 | ns | |
RDT = 20 kΩ | 167 | 185 | 203 | |||
RDT = 50 kΩ | 399 | 443 | 487 |