SLUSCJ9F June   2016  – November 2024 UCC21520

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in the UCC21520 and the UCC21520A
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead-Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Gate to Source Resistor Selection
        5. 9.2.2.5 Estimate Gate Driver Power Loss
        6. 9.2.2.6 Estimating Junction Temperature
        7. 9.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.7.1 Selecting a VCCI Capacitor
          2. 9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.7.3 Select a VDDB Capacitor
        8. 9.2.2.8 Dead Time Setting Guidelines
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Revision History

Changes from Revision E (December 2021) to Revision F (November 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Deleted 5ns maximum delay matching from Features sectionGo
  • Changed Typ propagation delay from 19ns to 33nsGo
  • Changed 10ns minmum pulse width to 20nsGo
  • Changed operating temperature range to junction temeperature rangeGo
  • Changed CMTI specification from 100V/ns to 125V/nsGo
  • Changed surge immunity value from 12.8kV to 10kVGo
  • Deleted bullet on isolation barrier life >40 yearsGo
  • Deleted "Rejects input pulses and noise transients shorter than 5ns"Go
  • Updated safety certifications to latest standardsGo
  • Deleted CSA certificationGo
  • Updated Description section to match new spec valuesGo
  • Updated DT pin description to recommend ≤1nF capacitor on DT pinGo
  • Changed DT pin Min resistor recommendations from 500Ω to 2kΩGo
  • Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
  • Deleted ambient temperature specGo
  • Changed Max junction temp to 150CGo
  • Updated values from RθJA = 67.3°C/W, RθJC(top) = 34.4°C/W, RθJB = 32.1°C/W, ψJT = 18°C/W, ψJB = 31.6°C/W to RθJA = 69.8°C/W, RθJC(top) = 33.1°C/W, RθJB = 36.9°C/W, ψJT = 22.2°C/W, ψJB = 36°C/WGo
  • Updated values from PD = 1.05W, PDI = 0.05W, PDA/PDB = 0.5W to PD = 950mW, PDI = 50mW, PDA/PDB = 450mWGo
  • Updated values from DTI = 21mm, VIOSM = 8000VPK to DTI = 17mm, VIOSM = 10000VPK and added VIMP = 7692VPKGo
  • Deleted safety related certifications sectionGo
  • Updated values from IS = 75mA/36mA, PS = 50mW/900mW/900mW/1850mW to IS = 58mA/34mA, PS = 50mW/870mW/870mW/1790mWGo
  • Changed test condition from VDDA=VDDB=12V to VDDA=VDDB=15VGo
  • Updated IVCCI quiescent current spec 1.4mA typical value to 1.5mA typicalGo
  • Updated IVDDA/IVDDB quiescent current spec Max value from 1.8mA to 2.5mAGo
  • Updated IVCCI operating current Typ value from 2.0mA to 3.0mA and added Max value 3.5mAGo
  • Added IVDDA/IVDDB operating current Max = 4.2mAGo
  • Updated values from Rising threshold Min = 8.3V, Typ = 8.7V, Max = 9.2V to Min = 7.7V, Typ = 8.5V, Max = 8.9VGo
  • Updated values from Falling threshold Min = 7.8V, Typ = 8.2V, Max = 8.7V to Min = 7.2V, Typ = 7.9V, Max = 8.4VGo
  • Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
  • Updated Input high threshold Min value from 1.6V to 1.2VGo
  • Changed output voltage at high state spec from 11.95V Typ to 14.95V Typ. Changed test condition from VDDA=VDDB=15V to VDDA=VDDB=12V. Go
  • Deleted Dead time parameter from Electrical Characteristics and added new Timing RequirementsGo
  • Changed propagation delay TPDHL and TPDLH from Min=14ns, Typ = 19ns, Max = 30ns to Min=26ns. Typ = 33ns, Max = 45nsGo
  • Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
  • Added VCCI power up delayGo
  • Updated VDDA/VDDB power-up delay from Max = 100us to 10usGo
  • Updated CMTI from Min = 100V/ns to 125V/nsGo
  • Updated insulation and thermal curves to match updated characteristicsGo
  • Updated typical characteristics figuresGo
  • Updated Power-up UVLO Delay to OUTPUT section to match device electrical characteristics Go
  • Changed the Functional Block Diagram to add deglitch filter blockGo
  • Changed DISABLE logic; DISABLE left open will pull outputs lowGo
  • Added paragraph on minimum pulse width to Output Stage sectionGo
  • Updated ESD diode structureGo
  • Updated DT Pin Connected to a Programming Resistor Between DT and GND Pins section to recommend <=1nF capacitor on DT pin. Go
  • Updated typical schematic DT pin capacitor recommendation Go
  • Updated Dead Time Setting Guidelines section to recommend <=1nF capacitor on DT pin. Go

Changes from Revision D (March 2020) to Revision E (December 2021)

Changes from Revision C (December 2019) to Revision D (March 2020)

  • Changed DT pin descriptionGo
  • Changed DT pin configuration recommendations Go
  • Added update to bootstrap circuit recommendationsGo
  • Added update to gate resistor selection recommendations Go
  • Added gate to source resistor recommendation Go
  • Added update to Cboot selection recommendations Go