SLUSCJ9F June   2016  – November 2024 UCC21520

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in the UCC21520 and the UCC21520A
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead-Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Gate to Source Resistor Selection
        5. 9.2.2.5 Estimate Gate Driver Power Loss
        6. 9.2.2.6 Estimating Junction Temperature
        7. 9.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.7.1 Selecting a VCCI Capacitor
          2. 9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.7.3 Select a VDDB Capacitor
        8. 9.2.2.8 Dead Time Setting Guidelines
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.12 Typical Characteristics

VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

UCC21520 UCC21520A Per Channel Current Consumption vs Frequency (No Load, VDD = 15 V or 25 V)
Figure 6-4 Per Channel Current Consumption vs Frequency (No Load, VDD = 15 V or 25 V)
UCC21520 UCC21520A Per Channel Current Consumption (IVDDA/B) vs Frequency (10-nF Load, VDD = 15 V or 25 V)
Figure 6-6 Per Channel Current Consumption (IVDDA/B) vs Frequency (10-nF Load, VDD = 15 V or 25 V)
UCC21520 UCC21520A Per Channel (IVDDA/B) Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching)
Figure 6-8 Per Channel (IVDDA/B) Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching)
UCC21520 UCC21520A Rising and Falling Times vs Load (VDD = 15 V)
A.
Figure 6-10 Rising and Falling Times vs Load (VDD = 15 V)
UCC21520 UCC21520A Propagation Delay vs Temperature
Figure 6-12 Propagation Delay vs Temperature
UCC21520 UCC21520A Pulse Width Distortion vs Temperature
A.
Figure 6-14 Pulse Width Distortion vs Temperature
UCC21520 UCC21520A Propagation Delay Matching (tDM) vs Temperature
Figure 6-16 Propagation Delay Matching (tDM) vs Temperature
UCC21520 UCC21520A VDD 5-V UVLO Threshold vs Temperature
Figure 6-18 VDD 5-V UVLO Threshold vs Temperature
UCC21520 UCC21520A VDD 8-V UVLO Threshold vs Temperature
Figure 6-20 VDD 8-V UVLO Threshold vs Temperature
UCC21520 UCC21520A IN/DIS Low Threshold
Figure 6-22 IN/DIS Low Threshold
UCC21520 UCC21520A Dead Time vs Temperature (with RDT = 20 kΩ and 100 kΩ)
Figure 6-24 Dead Time vs Temperature (with RDT = 20 kΩ and 100 kΩ)
UCC21520 UCC21520A Typical Output Waveforms
Figure 6-26 Typical Output Waveforms
UCC21520 UCC21520A Per Channel Current Consumption (IVDDA/B) vs Frequency (1-nF Load, VDD = 15 V or 25 V)
Figure 6-5 Per Channel Current Consumption (IVDDA/B) vs Frequency (1-nF Load, VDD = 15 V or 25 V)
UCC21520 UCC21520A Per Channel (IVDDA/B) Supply Current vs Temperature (No Load, Different Switching Frequencies)
Figure 6-7 Per Channel (IVDDA/B) Supply Current vs Temperature (No Load, Different Switching Frequencies)
UCC21520 UCC21520A IVCCI Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching)
A.
Figure 6-9 IVCCI Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching)
UCC21520 UCC21520A Output Resistance vs Temperature
Figure 6-11 Output Resistance vs Temperature
UCC21520 UCC21520A Propagation Delay vs VCCI
Figure 6-13 Propagation Delay vs VCCI
UCC21520 UCC21520A Propagation Delay Matching (tDM) vs VDD
Figure 6-15 Propagation Delay Matching (tDM) vs VDD
UCC21520 UCC21520A VDD 5-V UVLO Hysteresis vs Temperature
Figure 6-17 VDD 5-V UVLO Hysteresis vs Temperature
UCC21520 UCC21520A VDD 8-V UVLO Hysteresis vs Temperature
Figure 6-19 VDD 8-V UVLO Hysteresis vs Temperature
UCC21520 UCC21520A IN/DIS Hysteresis vs Temperature
Figure 6-21 IN/DIS Hysteresis vs Temperature
UCC21520 UCC21520A IN/DIS High Threshold
Figure 6-23 IN/DIS High Threshold
UCC21520 UCC21520A Dead Time Matching vs Temperature (with RDT = 20 kΩ and 100 kΩ)
Figure 6-25 Dead Time Matching vs Temperature (with RDT = 20 kΩ and 100 kΩ)