SLUSCO3B
September 2016 – December 2021
UCC21521
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety-Limiting Values
6.9
Electrical Characteristics
6.10
Switching Characteristics
6.11
Insulation Characteristics Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Propagation Delay and Pulse Width Distortion
7.2
Rising and Falling Time
7.3
Input and Enable Response Time
7.4
Programmable Dead Time
7.5
Powerup UVLO Delay to OUTPUT
7.6
CMTI Testing
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VDD, VCCI, and Under Voltage Lock Out (UVLO)
8.3.2
Input and Output Logic Table
8.3.3
Input Stage
8.3.4
Output Stage
8.3.5
Diode Structure in UCC21521
8.4
Device Functional Modes
8.4.1
Enable Pin
8.4.2
Programmable Dead Time (DT) Pin
8.4.2.1
Tying the DT Pin to VCC
8.4.2.2
DT Pin Connected to a Programming Resistor between DT and GND Pins
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Designing INA/INB Input Filter
9.2.2.2
Select External Bootstrap Diode and its Series Resistor
9.2.2.3
Gate Driver Output Resistor
9.2.2.4
Gate to Source Resistor Selection
9.2.2.5
Estimate Gate Driver Power Loss
9.2.2.6
Estimating Junction Temperature
9.2.2.7
Selecting VCCI, VDDA/B Capacitor
9.2.2.7.1
Selecting a VCCI Capacitor
9.2.2.7.2
Selecting a VDDA (Bootstrap) Capacitor
9.2.2.7.3
Select a VDDB Capacitor
9.2.2.8
Dead Time Setting Guidelines
9.2.2.9
Application Circuits with Output Stage Negative Bias
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Third-Party Products Disclaimer
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Certifications
12.4
Receiving Notification of Documentation Updates
12.5
Support Resources
12.6
Trademarks
12.7
Electrostatic Discharge Caution
12.8
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DW|16
MSOI003I
Thermal pad, mechanical data (Package|Pins)
DW|16
QFND505A
Orderable Information
slusco3b_oa
slusco3b_pm
1
Features
Universal: dual low-side, dual high-side or half-bridge driver
Operating temperature range –40 to +125°C
Switching parameters:
19-ns typical propagation delay
10-ns minimum pulse width
5-ns maximum delay matching
6-ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater than 100 V/ns
Surge immunity up to 12.8 kV
Isolation barrier life >40 years
4-A peak source, 6-A peak sink output
TTL and CMOS compatible inputs
3-V to 18-V input VCCI range to interface with both digital and analog controllers
Up to 25-V VDD output drive supply
5-V, 8-V, 12-V VDD UVLO options
Programmable overlap and dead time
Rejects input pulses and noise transients shorter than 5 ns
Fast enable for power sequencing
Wide body SOIC-16 (DW) package
Safety-related certifications:
8000-V
PK
reinforced isolation per DIN V VDE V 0884-11:2017-01
5700-V
RMS
Isolation for 1 minute per UL 1577
CSA certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 end equipment standards
CQC certification per GB4943.1-2011