SLUSDG3F August   2018  – September 2024 UCC21530-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Enable Response Time
    4. 6.4 Programable Dead Time
    5. 6.5 Power-Up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in UCC21530-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select Dead Time Resistor and Capacitor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Estimate Gate Driver Power Loss
        5. 8.2.2.5 Estimating Junction Temperature
        6. 8.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.6.1 Selecting a VCCI Capacitor
        7. 8.2.2.7 Other Application Example Circuits
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15 (for 8V and 12V UVLO variants) or 20V (for 17V UVLO variant), 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, load capacitance COUT = 0 pF, TJ = –40°C to +150°C. (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRISE Output rise time, 20% to 80% measured points COUT = 1.8 nF 6 16 ns
tFALL Output fall time, 90% to 10% measured points COUT = 1.8 nF 7 12 ns
tPWmin Minimum pulse width Output off for less than minimum, COUT = 0pF 20 ns
tPDHL Propagation delay from INx to OUTx falling edges 26 33 45 ns
tPDLH Propagation delay from INx to OUTx rising edges 26 33 45 ns
tPWD  Pulse width distortion |tPDLH – tPDHL| 6 ns
tDM Propagation Delay Matching for Dual Channel Driver Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|		 6.5 ns
Input Pulse Width = 100ns, 500kHz, TJ = -10°C to +150°C
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|		 5 ns
tVCCI+ to OUT VCCI Power-up Delay Time: UVLO Rise to OUTA, OUTB INA or INB tied to VCCI 50 μs
tVDD+ to OUT VDDA. VDDB Power-up Delay Time: UVLO Rise to OUTA, OUTB INA or INB tied to VCCI 10 μs
|CMH| High-level common-mode transient immunity (See Section 6.6) Slew rate of GND versus VSSA/B, INA and INB both are tied to GND or VCCI; VCM = 1500V 125 V/ns
|CML| Low-level common-mode transient immunity (See Section 6.6) Slew rate of GND versus VSSA/B, INA and INB both are tied to GND or VCCI; VCM = 1500V 125 V/ns