SLUSDC0D October   2018  – November 2024 UCC21530

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Enable Response Time
    4. 6.4 Programable Dead Time
    5. 6.5 Power-Up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in UCC21530-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select Dead Time Resistor and Capacitor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Estimate Gate Driver Power Loss
        5. 8.2.2.5 Estimating Junction Temperature
        6. 8.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.6.1 Selecting a VCCI Capacitor
        7. 8.2.2.7 Other Application Example Circuits
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Revision History

Changes from Revision C (November 2021) to Revision D (November 2024)

  • Changed typical propagation delay from 19ns to 33nsGo
  • Changed minimum pulse width from 10ns to 20nsGo
  • Deleted bullet on 5-ns maximum delay matchingGo
  • Changed CMTI from greater than 100V/ns to greater than 125V/nsGo
  • Deleted bullet on >40 years isolation barrierGo
  • Deleted bullet on rejecting shorter than 5ns input pulsesGo
  • Changed operating temperature to new range of junction temperatureGo
  • Updated certifications to latest standards. Removed CSA certificationGo
  • Deleted sentence on best-in-class propagation delay and PWDGo
  • Changed minimum 100V/ns CMTI to 125V/nsGo
  • Changed recommended DT pin condition and capacitor size on DT pinGo
  • Changing all -0.5V minimum to -0.3V to keep consistent with newly released datasheetsGo
  • Changing all absolute maximum value from supply+0.5V to supply+0.3V to keep consistent with newly released datasheetsGo
  • Changed input signal voltage transient test condition to 50ns and absolute minimum to -5VGo
  • Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
  • Changed 12V-UVLO recommended minimum VDDA/B voltage from 14.7V to 13.5VGo
  • Deleted ambient temperature specGo
  • Changed Max junction temp to 150CGo
  • Updated values from RθJA = 68.3°C/W, RθJC(top) = 31.7°C/W, RθJB = 27.6°C/W, ψJT = 17.7°C/W, ψJB = 27°C/W to RθJA = 74.1°C/W, RθJC(top) = 34.1°C/W, RθJB = 32.8°C/W, ψJT = 23.7°C/W, ψJB = 32.1°C/WGo
  • Updated values from PD = 1810mW, PDI = 0.05W, PDA/PDB = 880mW to PD = 950mW, PDI = 50mW, PDA/PDB = 450mW. Changed test condition.Go
  • Updated values from DTI = 21mm, VIOSM = 8000VPK to DTI = 17mm, VIOSM = 10000VPK and added VIMP = 7692VPKGo
  • Deleted safety related certifications sectionGo
  • Updated values from IS = 58mA/35mA, PS = 50mW/880mW/880mW/1810mW to IS = 53mA/32mA, PS = 50mW/800mW/800mW/1650mWGo
  • Changed VCCI quiescent current typical from 1.4mA to 1.5mAGo
  • Updated IVDDA/IVDDB quiescent current spec Max value from 1.8mA to 2.5mAGo
  • Updated IVCCI operating current Typ value from 2.0mA to 3.0mA and added Max value 3.5mAGo
  • Changed IVDDA/IVDDB operating current Typ from 3mA to 2.5mA and added Max = 4.2mAGo
  • Updated values from Rising threshold Min = 8V, Typ = 8.5V, Max = 9V to Min = 7.7V, Typ = 8.5V, Max = 8.9VGo
  • Updated values from Falling threshold Min = 7.5V, Typ = 8V, Max = 8.5V to Min = 7.2V, Typ = 7.9V, Max = 8.4VGo
  • Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
  • Updated values from Rising threshold Min = 12.5V, Typ = 13.5V, Max = 14.5V to Min = 11.7V, Typ = 12.5V, Max = 13.3VGo
  • Updated values from Rising threshold Min = 11.5V, Typ = 12.5V, Max = 13.5V to Min = 10.7V, Typ = 11.5V, Max = 12.3VGo
  • Updated Input high threshold Min value from 1.6V to 1.2VGo
  • Deleted enable high and low thresholdGo
  • Updated Deadtime parameter by moving to new Timing Requirements table and added more parametersGo
  • Changed propagation delay TPDHL and TPDLH from Min = 14ns, Typ = 19ns, Max = 30ns to Min = 26ns, Typ = 33ns, Max = 45nsGo
  • Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
  • Deleted VCCI power up delay typical 40us and added max 50usGo
  • Updated VDDA/VDDB power-up delay from Typ = 50us to Max=10usGo
  • Updated CMTI from Min = 100V/ns to 125V/nsGo
  • Updated insulation and thermal curves to match updated characteristicsGo
  • Updated typical characteristics figuresGo
  • Updated UVLO timing delaysGo
  • Added driver stage deglitch filter block in functional block diagramGo
  • Changed ENABLE logic; ENABLE left open will pull outputs lowGo
  • Added paragraph on minimum pulse width to Output Stage sectionGo
  • Updated ESD diode structureGo
  • Changed recommended DT capacitor size from >2.2nF to ≤1nFGo
  • Changed recommended DT capacitor size in schematicGo
  • Changed DT capacitor size to ≤1nFGo
  • Changed DT capacitor size recommendation from >=2.2nF to ≤1nFGo

Changes from Revision B (December 2019) to Revision C (November 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed maximum pulse-width distortion value in Features section from "5 ns" to "6 ns"Go