SLUSEW9D May   2023  – June 2024 UCC21551

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Enable Response Time
    4. 6.4 Programmable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21551x
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin
      2. 7.4.2 Programmable Dead-Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

UCC21551 DW Package16-Pin SOICTop View Figure 4-1 DW Package16-Pin SOICTop View
UCC21551 DWK Package14-Pin SOICTop View Figure 4-2 DWK Package14-Pin SOICTop View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
EN 5 I Enable both driver outputs if asserted high, disable both outputs if set low. It is recommended to tie this pin to VCCI if not used to achieve better noise immunity. This pin is internally pulled low if left floating. It is recommended to use an RC filter on EN pin to filter high frequency noise, with R = 0 Ω to 100 Ω and C = 100 pF to 1000 pF.
DT 6 I DT pin configurations:
  • DT pin float or short to VCCI disables dead time interlock function (allows outputs to overlap)
  • Place 1.7-kΩ to 100-kΩ resistor (RDT) between DT and GND to set minimum dead time between driver outputs
  • Place 0-Ω to 150-Ω resistor, or short DT pin to GND to have two outputs interlocked
  • TI does not recommend bypassing this pin with a ceramic capacitor >1nF
GND 4 G Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA 1 I Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to use an RC filter on INA to filter high frequency noise, with R = 10 Ω to 100 Ω and C = 10 pF to 100 pF.
INB 2 I Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to use an RC filter on INB to filter high frequency noise, with R = 10 Ω to 100 Ω and C = 10 pF to 100 pF.
NC 7 – No Internal connection.
NC 12 – No internal connection.
NC 13 – No internal connection.
OUTA 15 O Output of driver A. Connect to the gate of the A channel transistor through a gate resistor.
OUTB 10 O Output of driver B. Connect to the gate of the B channel transsitor through a gate resistor.
VCCI 3 P Primary-side supply voltage. Locally decouple to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA 16 P Secondary-side power for driver A. Locally decouple to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB 11 P Secondary-side power for driver B. Locally decouple to VSSB using low ESR/ESL capacitor located as close to the device as possible.
VSSA 14 G Ground reference for secondary side A channel.
VSSB 9 G Ground reference for secondary side B channel.
(1) P = Power, G = Ground, I = Input, O = Output