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  • UCC21710-Q1 10A Source/Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI

    • SLUSDH8D January   2019  – June 2024 UCC21710-Q1

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  • UCC21710-Q1 10A Source/Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay
      1. 6.1.1 Regular Turn-OFF
    2. 6.2 Input Deglitch Filter
    3. 6.3 Active Miller Clamp
      1. 6.3.1 Internal On-chip Active Miller Clamp
    4. 6.4 Under Voltage Lockout (UVLO)
      1. 6.4.1 VCC UVLO
      2. 6.4.2 VDD UVLO
    5. 6.5 OC (Over Current) Protection
      1. 6.5.1 OC Protection with Soft Turn-OFF
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply
      2. 7.3.2  Driver Stage
      3. 7.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 7.3.4  Active Pulldown
      5. 7.3.5  Short Circuit Clamping
      6. 7.3.6  Internal Active Miller Clamp
      7. 7.3.7  Overcurrent and Short Circuit Protection
      8. 7.3.8  Soft Turn-off
      9. 7.3.9  Fault ( FLT, Reset and Enable ( RST/EN)
      10. 7.3.10 Isolated Analog to PWM Signal Function
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input filters for IN+, IN- and RST/EN
        2. 8.2.2.2 PWM Interlock of IN+ and IN-
        3. 8.2.2.3 FLT, RDY and RST/EN Pin Circuitry
        4. 8.2.2.4 RST/EN Pin Control
        5. 8.2.2.5 Turn on and turn off gate resistors
        6. 8.2.2.6 Overcurrent and Short Circuit Protection
          1. 8.2.2.6.1 Protection Based on Power Modules with Integrated SenseFET
          2. 8.2.2.6.2 Protection Based on Desaturation Circuit
          3. 8.2.2.6.3 Protection Based on Shunt Resistor in Power Loop
        7. 8.2.2.7 Isolated Analog Signal Sensing
          1. 8.2.2.7.1 Isolated Temperature Sensing
          2. 8.2.2.7.2 Isolated DC Bus Voltage Sensing
        8. 8.2.2.8 Higher Output Current Using an External Current Buffer
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DW|16
    • MSOI003I
Thermal pad, mechanical data (Package|Pins)
  • DW|16
    • QFND505A
Orderable Information
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  • slusdh8d_pm
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Data Sheet

UCC21710-Q1 10A Source/Sink Reinforced Isolated Single Channel Gate Driver
for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI

1 Features

  • 5.7kVRMS single channel isolated gate driver
  • AEC-Q100 qualified for automotive applications
    • Device temperature grade 1: -40°C to +125°C ambient operating temperature range
  • SiC MOSFETs and IGBTs up to 2121Vpk
  • 33V maximum output drive voltage (VDD-VEE)
  • ±10A drive strength and split output
  • 150V/ns minimum CMTI
  • 270ns response time fast overcurrent protection
  • 4A internal active miller clamp
  • 400mA soft turn-off when fault happens
  • Isolated analog sensor with PWM output for
    • Temperature sensing with NTC, PTC or thermal diode
    • High voltage DC-Link or phase voltage
  • Alarm FLT on over current and reset from RST/EN
  • Fast enable/disable response on RST/EN
  • Reject <40ns noise transient and pulse on input pins
  • 12V VDD UVLO with power good on RDY
  • Inputs/outputs with over/under-shoot transient voltage Immunity up to 5V
  • 130ns (maximum) propagation delay and 30ns (maximum) pulse/part skew
  • SOIC-16 DW package with creepage and clearance distance > 8mm
  • Operating junction temperature –40°C to 150°C
  • Safety-related certifications:
    • Reinforced insulation per DIN EN IEC 60747-17(VDE 0884-17)
    • UL 1577 component recognition program

2 Applications

  • Traction inverter for EVs
  • On-board charger and charging pile
  • DC/DC Converter for HEV/EVs

3 Description

The UCC21710-Q1 is a galvanic isolated single channel gate driver designed for up to 1700-V SiC MOSFETs and IGBTs with advanced protection features, best-in-class dynamic performance and robustness. UCC21710-Q1 has up to ±10A peak source and sink current.

The input side is isolated from the output side with SiO2 capacitive isolation technology, supporting up to 1.5kVRMS working voltage, 12.8kVPK surge immunity with longer than 40 years Isolation barrier life, as well as providing low part-to-part skew , and >150V/ns common mode noise immunity (CMTI).

The UCC21710-Q1 includes the state-of-the-art protection features, such as fast overcurrent and short circuit detection, shunt current sensing support, fault reporting, active Miller clamp, and input and output side power supply UVLO to optimize SiC and IGBT switching behavior and robustness. The isolated analog to PWM sensor can be used for easier temperature or voltage sensing, further increasing the drivers' versatility and simplifying the system design effort, size and cost.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
UCC21710-Q1 DW (SOIC-16) 10.3mm × 7.5mm
(1) For all available packages, see Section 13.
UCC21710-Q1 Device Pin Configuration Device Pin Configuration

4 Pin Configuration and Functions

UCC21710-Q1 UCC21710-Q1DW SOIC (16)Top View Figure 4-1 UCC21710-Q1DW SOIC (16)Top View
Table 4-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
AIN 1 I Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if unused.
OC 2 I Over current detection pin, support lower threshold for SenseFET, DESAT, and shunt resistor sensing. Tie to COM if unused.
COM 3 P Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET
OUTH 4 O Gate driver output pull up
VDD 5 P Positive supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin.
OUTL 6 O Gate driver output pull down
CLMPI 7 I Internal Active miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or tie to VEE if unused.
VEE 8 P Negative supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin.
GND 9 P Input power supply and logic ground reference
IN+ 10 I Non-inverting gate driver control input. Tie to VCC if unused.
IN– 11 I Inverting gate driver control input. Tie to GND if unused.
RDY 12 O Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals
FLT 13 O Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be paralleled with other faults
RST/EN 14 I The RST/EN serves two purposes:
1) Enable / shutdown of the output side. The FET is turned off by a regular turn-off, if terminal EN is set to low;
2) Resets the DESAT condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A reset of signal FLT is asserted at the rising edge of terminal RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to low.
VCC 15 P Input power supply from 3V to 5.5V. Bypass with a >1-μF capacitor to GND. Place decoupling capacitor close to the pin.
APWM 16 O Isolated Analog Sensing PWM output. Leave floating if unused.
(1) P = Power, G = Ground, I = Input, O = Output

5 Specifications

 
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