The UCC21738-Q1 is a galvanic isolated single channel gate driver designed for SiC MOSFETs and IGBTs up to 2121-V DC operating voltage with advanced protection features, best-in-class dynamic performance and robustness. The device has up to ±10-A peak source and sink currents.
The input side is isolated from the output side with SiO2 capacitive isolation technology, supporting up to 1.5-kVRMS working voltage, 12.8-kVPK surge immunity with longer than 40 years isolation barrier life, as well as providing low part-to-part skew, and >150-V/ns common-mode transient immunity (CMTI).
The UCC21738-Q1 includes the state-of-art protection features, such as fast overcurrent and short circuit detection, shunt current sensing support, fault reporting, active Miller clamp, input and output side power supply UVLO to optimize SiC and IGBT switching behavior and robustness. The ASC feature can be utilized to force ON power switch during system failure events, further increasing the drivers' versatility and simplifying the system design effort, size, and cost.
PART NUMBER(1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC21738-Q1 | DW SOIC-16 | 10.3 mm × 7.5 mm |
DATE | REVISION | NOTES |
---|---|---|
September 2023 | * | Initial Release |
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ASC | 1 | I | Active high to enable active short circuit function to force output high during system failure events. Tie to COM if unused. |
OC | 2 | I | Overcurrent detection pin for SenseFET, DESAT, and shunt resistor sensing. Tie to COM if unused. |
COM | 3 | P | Common ground reference. Connect to emitter pin for IGBT and source pin for SiC-MOSFET |
OUTH | 4 | O | Gate driver output pull up |
VDD | 5 | P | Positive supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin. |
OUTL | 6 | O | Gate driver output pull down |
CLMPE | 7 | O | External active Miller clamp control. Connect this pin to the gate of the external Miller clamp MOSFET. Leave floating if unused. |
VEE | 8 | P | Negative supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin. |
GND | 9 | P | Input power supply and logic ground reference |
IN+ | 10 | I | Noninverting gate driver control input. Tie to VCC if unused. |
IN– | 11 | I | Inverting gate driver control input. Tie to GND if unused. |
RDY | 12 | O | Power good for VCC-GND, VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals. |
FLT | 13 | O | Active low fault alarm output upon overcurrent or short circuit. FLT is in open drain configuration and can be paralleled with other faults. |
RST/EN | 14 | I | The RST/EN serves two purposes: 1) Enable or shutdown the output side. The FET is turned off by a regular turn-off if EN is set to low; 2) Resets the OC condition signaled on FLT pin if RST/EN is set to low for more than 1000 ns. A reset of signal FLT is asserted at the rising edge of RST/EN. For automatic reset function, this pin only serves to enable or shutdown the output side. The FET is turned off by a regular turn-off, if terminal EN is set to low. Tie to IN+ for automatic reset. |
VCC | 15 | P | Input power supply from 3 V to 5.5 V. Bypass with a >1-μF capacitor to GND. Place decoupling capacitor close to the pin. |
APWM | 16 | O | Isolated PWM output monitoring ASC pin status. Leave floating if unused. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | VCC - GND | –0.3 | 6 | V |
VDD | VDD - COM | –0.3 | 36 | V |
VEE | VEE - COM | –17.5 | 0.3 | V |
VMAX | VDD - VEE | –0.3 | 36 | V |
IN+, IN-, RST/EN | DC | GND–0.3 | VCC | V |
Transient, less than 100 ns (2) | GND–5.0 | VCC+5.0 | V | |
ASC | Reference to COM | –0.3 | 6 | V |
OC | Reference to COM | –0.3 | 6 | V |
OUTH, OUTL | DC | VEE–0.3 | VDD | V |
Transient, less than 100 ns (2) | VEE–5.0 | VDD+5.0 | V | |
CLMPE | Reference to VEE | –0.3 | 5 | V |
RDY, FLT, APWM | GND–0.3 | VCC | V | |
IFLT, IRDY | FLT and RDY pin input current | 20 | mA | |
IAPWM | APWM pin output current | 20 | mA | |
TJ | Junction Temperature | –40 | 150 | °C |
Tstg | Storage Temperature | –65 | 150 | °C |