SLUSEM9A September   2022  – June 2024 UCC21755-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay
      1. 6.1.1 Non-Inverting and Inverting Propagation Delay
    2. 6.2 Input Deglitch Filter
    3. 6.3 Active Miller Clamp
      1. 6.3.1 Internal On-Chip Active Miller Clamp
    4. 6.4 Undervoltage Lockout (UVLO)
      1. 6.4.1 VCC UVLO
      2. 6.4.2 VDD UVLO
    5. 6.5 Desaturation (DESAT) Protection
      1. 6.5.1 DESAT Protection with Soft Turn-OFF
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply
      2. 7.3.2  Driver Stage
      3. 7.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 7.3.4  Active Pulldown
      5. 7.3.5  Short Circuit Clamping
      6. 7.3.6  Internal Active Miller Clamp
      7. 7.3.7  Desaturation (DESAT) Protection
      8. 7.3.8  Soft Turn-Off
      9. 7.3.9  Fault (FLT), Reset and Enable (RST/EN)
      10. 7.3.10 Isolated Analog to PWM Signal Function
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filters for IN+, IN-, and RST/EN
        2. 8.2.2.2 PWM Interlock of IN+ and IN-
        3. 8.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 8.2.2.4 RST/EN Pin Control
        5. 8.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 8.2.2.6 Overcurrent and Short Circuit Protection
        7. 8.2.2.7 Isolated Analog Signal Sensing
          1. 8.2.2.7.1 Isolated Temperature Sensing
          2. 8.2.2.7.2 Isolated DC Bus Voltage Sensing
        8. 8.2.2.8 Higher Output Current Using an External Current Buffer
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

UCC21755-Q1 UCC21755-Q1 DW SOIC (16)Top View Figure 4-1 UCC21755-Q1 DW SOIC (16)Top View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AIN 1 I Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if unused.
DESAT 2 I Desaturation current protection input. Tie to COM if unused.
COM 3 P Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET
OUTH 4 O Gate driver output pullup
VDD 5 P Positive supply rail for gate drive voltage. Bypass with a >10-µF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin.
OUTL 6 O Gate driver output pulldown
CLMPI 7 I Internal Active Miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or tie to VEE if unused.
VEE 8 P Negative supply rail for gate drive voltage. Bypass with a >10-µF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin.
GND 9 P Input power supply and logic ground reference
IN+ 10 I Non-inverting gate driver control input. Tie to VCC if unused.
IN– 11 I Inverting gate driver control input. Tie to GND if unused.
RDY 12 O Power good for VCC-GND and VDD-COM. RDY is open-drain configuration and can be paralleled with other RDY signals.
FLT 13 O Active low fault alarm output upon overcurrent or short circuit. FLT is in open-drain configuration and can be paralleled with other faults.
RST/EN 14 I The RST/EN serves two purposes:
1) Enables or shuts down the output side. The FET is turned off by a regular turn-off, if pin EN is set to low;
2) Resets the DESAT condition signaled on the FLT pin if the pin RST/EN is set to low for more than 1000 ns. A reset of signal FLT is asserted at the rising edge of pin RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable or shutdown the output side. The FET is turned off by a regular turn-off, if pin EN is set to low. Tie to IN+ for automatic reset.
VCC 15 P Input power supply from 3 V to 5.5 V. Bypass with a >1-µF capacitor to GND. Place decoupling capacitor close to the pin.
APWM 16 O Isolated analog sensing PWM output. Leave floating if unused.