SLUSEM9A
September 2022 – June 2024
UCC21755-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Power Ratings
5.6
Insulation Specifications
5.7
Safety Limiting Values
5.8
Electrical Characteristics
5.9
Switching Characteristics
5.10
Insulation Characteristics Curves
5.11
Typical Characteristics
6
Parameter Measurement Information
6.1
Propagation Delay
6.1.1
Non-Inverting and Inverting Propagation Delay
6.2
Input Deglitch Filter
6.3
Active Miller Clamp
6.3.1
Internal On-Chip Active Miller Clamp
6.4
Undervoltage Lockout (UVLO)
6.4.1
VCC UVLO
6.4.2
VDD UVLO
6.5
Desaturation (DESAT) Protection
6.5.1
DESAT Protection with Soft Turn-OFF
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Supply
7.3.2
Driver Stage
7.3.3
VCC and VDD Undervoltage Lockout (UVLO)
7.3.4
Active Pulldown
7.3.5
Short Circuit Clamping
7.3.6
Internal Active Miller Clamp
7.3.7
Desaturation (DESAT) Protection
7.3.8
Soft Turn-Off
7.3.9
Fault (FLT), Reset and Enable (RST/EN)
7.3.10
Isolated Analog to PWM Signal Function
7.4
Device Functional Modes
8
Applications and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input Filters for IN+, IN-, and RST/EN
8.2.2.2
PWM Interlock of IN+ and IN-
8.2.2.3
FLT, RDY, and RST/EN Pin Circuitry
8.2.2.4
RST/EN Pin Control
8.2.2.5
Turn-On and Turn-Off Gate Resistors
8.2.2.6
Overcurrent and Short Circuit Protection
8.2.2.7
Isolated Analog Signal Sensing
8.2.2.7.1
Isolated Temperature Sensing
8.2.2.7.2
Isolated DC Bus Voltage Sensing
8.2.2.8
Higher Output Current Using an External Current Buffer
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DW|16
MSOI003I
Thermal pad, mechanical data (Package|Pins)
DW|16
QFND505A
Orderable Information
slusem9a_oa
slusem9a_pm
1
Features
5.7kV
RMS
single-channel isolated gate driver
AEC-Q100 Qualified with the following results:
Device temperature grade 1: -40°C to +125°C ambient operating temperature range
Functional Safety Quality-Managed
Documentation available to aid functional safety system design
SiC MOSFETs and IGBTs up to 2121V
pk
33V maximum output drive voltage (VDD-VEE)
±10A drive strength and split output
150V/ns minimum CMTI
200ns response time fast DESAT protection with 5V threshold
4A internal active Miller clamp
400mA
soft turn-off when fault happens
Isolated analog sensor with PWM output for
Temperature sensing with NTC, PTC, or thermal diode
High voltage DC-link or phase voltage
Alarm
FLT
on overcurrent and reset from
RST
/EN
Fast enable/disable response on
RST
/EN
Reject <40ns noise transient and pulse on input pins
12V VDD UVLO with power good on RDY
Inputs/outputs with over- or under-shoot transient voltage immunity up to 5V
130ns (maximum) propagation delay and 30ns (maximum) pulse/part skew
SOIC-16 DW package with creepage and clearance distance > 8mm
Operating junction temperature –40°C to 150°C