SLUSDV7B October   2019  – March 2021 UCC23313-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Function
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay, rise time and fall time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Resistor
        2. 9.2.2.2 Gate Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
        5. 9.2.2.5 Selecting VCC Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWY|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Switching Characteristics

Unless otherwise noted, all typical values are at TA = 25°C, VCC-VEE= 30 V, VEE= GND. All min and max specifications are at recommended operating conditions (TJ = -40 to 150°C, IF(ON)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(OFF)= –5V to 0.8V)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Output-signal Rise Time Cg = 1nF
FSW = 20 kHz, (50% Duty Cycle)
VCC=15V
28 ns
tf Output-signal Fall Time 25 ns
tPLH Propagation Delay, Low to High 70 105 ns
tPHL Propagation Delay, High to Low 70 105 ns
tPWD Pulse Width Distortion |tPHL – tPLH| 35 ns
tsk(pp) Part-to-Part Skew in Propagation Delay Between any Two Parts(1) Cg = 1nF
FSW = 20 kHz, (50% Duty Cycle)
VCC=15V, IF=10mA
25 ns
tUVLO_rec UVLO Recovery Delay VCC Rising from 0V to 15V 20 30 µs
CMTIH Common-mode Transient Immunity (Output High) IF = 10 mA, VCM = 1500 V, VCC= 30 V, TA= 25°C 150 kV/µs
CMTIL Common-mode Transient Immunity (Output Low) VF = 0 V, VCM = 1500 V, VCC= 30 V, TA= 25°C 150 kV/µs
tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization.