SLUSF58A December   2023  – April 2024 UCC23525

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Thermal Derating Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Rise Time and Fall Time
    2. 6.2 IOH and IOL Testing
    3. 6.3 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
        4. 7.3.4.4 ESD Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Input Resistor
        2. 8.2.2.2 Gate Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VDD Capacitor
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWY|6
Thermal pad, mechanical data (Package|Pins)

8.2.2.2 Gate Driver Output Resistor

The external gate-driver resistors, RG(ON) and RG(OFF) are used to:

  1. Limit ringing caused by parasitic inductances and capacitances
  2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
  3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
  4. Reduce electromagnetic interference (EMI)

The output stage has a pull up with a peak source current of 5 A. Use Equation 2 to estimate the peak source current as an example.

Equation 2. I O H = m i n ⁡ [ 5 A , V D D - V G D F ( R O H + R G O N + R G F E T I N T )

where

  • RGON is the external turnon resistance.
  • RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will assume 0Ω for our example
  • IOH is the peak source current which is the minimum value between 5 A, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance.
  • VGDF is the forward voltage drop for each of the diodes in series with RGON and RGOFF. The diode drop for this example is 0.7 V.

In this example, the peak source current is approximately 1.15A as calculated in Equation 3.

Equation 3. I O H = min ⁡ 5 A , 15 2.5 Ω + 10 Ω + 0 Ω = 1.2 A

Similarly, use Equation 4 to calculate the peak sink current.

Equation 4. I O L = min ⁡ 5 A , V D D - V G D F R O L + R G O N | | R G O F F + R G F E T I N T

where

  • RGOFF is the external turnoff resistance.
  • IOL is the peak sink current which is the minimum value between 5 A, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum of 5 A and Equation 5.

Equation 5. I O L = min ⁡ 5 A , 15 - 0.7 0.7 Ω + 10 Ω | | 10 Ω + 0 Ω = 2.51 A

The diodes shown in series with RGOFF, in Figure 8-1 ensure the gate drive current flows through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from the VOUT pin to the power switch gate, with a resistance value approximately 20 times higher than RGOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω.

Note:

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the input capacitance of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.