SLUSD48C July   2018  – March 2022 UCC24624

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description, Continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Synchronous Rectifier Control
      3. 8.3.3 Turn-off Threshold Adjustment
      4. 8.3.4 Noise Immunity
        1. 8.3.4.1 On-Time Blanking
        2. 8.3.4.2 Off-Time Blanking
        3. 8.3.4.3 Two-Channel Interlock
        4. 8.3.4.4 SR Turn-on Re-arm
        5. 8.3.4.5 Adaptive Turn-on Delay
      5. 8.3.5 Gate Voltage Clamping
      6. 8.3.6 Standby Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MOSFET Selection
        2. 9.2.2.2 Snubber Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Turn-off Threshold Adjustment

When SR MOSFETs are implemented in LLC converters, they are often turned off too early, which creates long body diode conduction times. This results in more power loss, lower efficiency, and higher thermal stress.

The SR MOSFET early turn off is caused by the parasitic inductance in the SR voltage sensing path. As illustrated in Figure 8-5, the VDS voltage sensed by the synchronous rectifier controller (VSENSE) is the combination of the MOSFET on-state resistor voltage drop VSR, together with the voltage drops on parasitic inductors LD and LS. A better layout approach can minimize these parasitic inductors. However, the minimum value it can achieve is the package inductance of the SR MOSFET. With different packages, this parasitic inductance could vary from 2 to 10 nH.

GUID-91676EDD-2397-4AF8-84C5-1A079E5D1861-low.gifFigure 8-5 SR Controller Sensed Voltage

The overall sensed voltage can be represented by Equation 1.

Equation 1. GUID-3CF635B5-8B6F-446A-9836-81D0B97648F4-low.gif

Because of the sinusoidal current shape and high output current, the current slope (di/dt) creates a significant voltage drop across the package inductance. This causes the SR controller to detect a smaller voltage drop and turn off the SR MOSFET early.

To overcome this issue, UCC24624 implements several techniques.

First, the proportional gate drive feature is implemented. As discussed earlier, the proportional gate drive reduces the SR MOSFET gate drive voltage when the SR current is small, and increases its voltage drop. This increased voltage drop could overwhelm the offset voltage introduced by the package inductance. Thus the SR MOSFET conduction time is extended.

Second, the turn-off threshold is set at 10.5 mV, instead of typically being set as a negative threshold. Because of the high di/dt and unavoidable SR package inductance, positive voltage is always expected at zero SR current. The positive turn-off threshold allows the SR MOSFET to continue conduction toward the end of the intended conduction period without the concern of causing negative SR current because of anticipating the positive offset voltage on the package inductances.

Last, UCC24624 also allows the user to further increase the turn-off threshold to accommodate higher parasitic inductance MOSFET packages, such as TO-220 packages. As illustrated in Figure 8-6, UCC24624 has an internal current source that flows out of the VSS pin. By connecting a resistor from the VSS pin to the SR MOSFET source, the voltage drop across the external resistor increases the turn-off threshold. This increased turn-off threshold makes it more suitable for TO-220 packages. Less than 70-mV offset is recommended. When using the low inductance MOSFET packages, such as SON5x6, the external resistor is not needed because the proportional gate drive alone can take care of the offset caused by the smaller package inductance.

Note:

To ensure normal system operation, VSS pin must never be kept open.

GUID-15C0349B-5CE8-43FD-A4CF-CD2D7AFBCCA1-low.gifFigure 8-6 Adjustable Turn-off Threshold

The internal current source is at 330 µA and the external offset resistor value is recommended to be less than 212 Ω. The offset resistor Roffset can be calculated by using Equation 2 with the desired turn-off threshold VTHOFF.

Equation 2. GUID-A3A6DB28-C173-4E2C-B218-06383CB11166-low.gif

This added offset voltage only changes the SR turn-off threshold, while the proportional gate drive threshold remains the same.