SLUSD48C July   2018  – March 2022 UCC24624

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description, Continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Synchronous Rectifier Control
      3. 8.3.3 Turn-off Threshold Adjustment
      4. 8.3.4 Noise Immunity
        1. 8.3.4.1 On-Time Blanking
        2. 8.3.4.2 Off-Time Blanking
        3. 8.3.4.3 Two-Channel Interlock
        4. 8.3.4.4 SR Turn-on Re-arm
        5. 8.3.4.5 Adaptive Turn-on Delay
      5. 8.3.5 Gate Voltage Clamping
      6. 8.3.6 Standby Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MOSFET Selection
        2. 9.2.2.2 Snubber Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 Standby Mode

With stringent efficiency standards such as Department of Energy (DoE) level VI and Code of Conduct (CoC) version 5 tier 2, external power supplies are expected to maintain a very low standby power at no load conditions. It is essential for the SR controller to enter the low power standby mode to help reduce the no load power consumption.

During standby mode, the power converter loss allocation is quite different compared with heavy load. At heavier load, both conduction loss and switching loss are quite high. However, at light load, the conduction loss becomes insignificant and switching loss dominates the total loss. To help improve the standby power, modern power supply controllers often enter burst mode to save the switching loss. Furthermore, in each burst switching cycle, the energy delivered is maximized to minimize the number of switching cycles needed and further reduces the switching loss.

Traditionally, the SR controller monitors the SR conduction time to distinguish the normal operation mode or the standby mode. Because of the burst mode operation, the converter is equivalently operating at a much higher power level with long SR conduction time. This criterion is no longer suitable for the modern power supply controller designed for delivering minimum standby power.

Instead, in UCC24624, a frequency based standby mode detection is used. UCC24624 continuously monitors the average switching frequency of SR channel 1. Once the average switching frequency of channel 1 SR MOSFET drops below 9 kHz for 7.5 ms, the UCC24624 enters the standby mode, stops SR MOSFETs switching, and reduces its current consumption to IVDDSTBY. During standby mode, the SR switching cycle is continuously monitored through the body diode conduction. Once the average switching frequency is more than 15.6 kHz within 7.5 ms, the SR MOSFET operation is enabled again. UCC24624 ignores the first SR switching cycle after coming out of standby mode to make sure the SR isn't turned on in the middle of the switching cycle.