SLUSD48C July   2018  – March 2022 UCC24624

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description, Continued
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Synchronous Rectifier Control
      3. 8.3.3 Turn-off Threshold Adjustment
      4. 8.3.4 Noise Immunity
        1. 8.3.4.1 On-Time Blanking
        2. 8.3.4.2 Off-Time Blanking
        3. 8.3.4.3 Two-Channel Interlock
        4. 8.3.4.4 SR Turn-on Re-arm
        5. 8.3.4.5 Adaptive Turn-on Delay
      5. 8.3.5 Gate Voltage Clamping
      6. 8.3.6 Standby Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MOSFET Selection
        2. 9.2.2.2 Snubber Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

At VVDD = 12 VDC, CVG1 = CVG2 = 0 pF, CREG = 2.2 µF VVD1 = VVD2 = 0 V, –40°C ≤ TJ = TA ≤ +125°C, all voltages are with respect to PGND, and currents are positive into and negative out of the specified terminal, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS SUPPLY
IVDDSTART VDD current, REG under voltage VVDD = 4 V, VVD1 = VVD2 = 0 V 5 150 275 µA
IVDDRUN VDD current, run VVDD = 12 V 0.77 1.1 1.5 mA
VVDD = 5 V 0.7 1 1.5 mA
IVDDSTBY VDD current, standby mode VVDD = 12 V, 25℃ 110 180 200 µA
VVDD = 5 V, 25℃ 100 180 200 µA
VDDCLAMP VDD clamp voltage IVDD = 15 mA 24.75 27.5 29.5 V
UNDER VOLTAGE LOCKOUT (UVLO)
VREGON REG turn-on threshold 4.1 4.5 4.8 V
VREGOFF REG turn-off threshold 3.63 4 4.25 V
VREGHYST REG UVLO hysteresis VREGHYST = VREGON – VREGOFF 0.450 0.500 0.555 V
MOSFET VOLTAGE SENSING
VTHVGON SR turn-on threshold VVD1, or VVD2 falling –435 –265 –160 mV
VTHVGOFF SR turn-off threshold VVD1, or VVD2 rising 2 10.5 18 mV
IVS_OFFSET VSS pin offset current for turn-off threshold adjustment 260 330 400 µA
VTHPGD_LO Low-level regulation threshold –80 –35 0 mV
VTHPGD_HI High-level regulation threshold –165 –100 –40 mV
VTHARM SR turn-on re-arming threshold 1.4 1.5 1.7 V
IVDBIAS Bias current on VD1 or VD2 VVD1 = VVD2 = -150 mV –10 0 0.5 µA
GATE DRIVER
RVG_PU VG pull-up resistance 3.5 6.5 11.25 Ω
RVG_PD VG pull-down resistance 0.2 0.9 1.5 Ω
VGHI VG high clamp level IVG = 0 mA 9.95 10.9 11.68 V
VGUV VG output low voltage, VDD low bias VVDD = 4 V, IVG = 25 mA 1 20 100 mV
VGLO VG output low voltage VVDD = 12 V, IVG = 100 mA 5 100 175 mV
IVGSOURCE VG maximum source current(1) 0.9 1.5 2.4 A
IVGSINK VG maximum sink current(1) 2.6 4 6.7 A
REG SUPPLY
VREG REG pin regulation level VVDD = 15 V, ILOAD_REG = 0 mA 9.9 11 11.9 V
VREGLG Load regulation on REG VVDD = 15 V, ILOAD_REG = 0 mA to 30 mA 9 25 75 mV
VREGDO REG drop out on passthrough mode VVDD = 5 V, ILOAD_REG = 0 mA to 10 mA 0.1 0.28 0.5 V
IREGSC REG short circuit current VVDD = 12 V, VREG = 0 V 4.5 9.5 13 mA
IREGLIM REG current limit VVDD = 12 V, VREG = 8 V 41 60 95 mA
(1) Ensured by design. Not production tested.