The UCC24630 SR controller is a high-performance controller and driver for N-channel MOSFET power devices used for secondary-side synchronous rectification.
The combination of controller and MOSFET emulates a near-ideal diode rectifier. This solution not only directly reduces power dissipation of the rectifier but also reduces primary-side losses as well, due to compounding of efficiency gains.
Utilizing a volt-second balancing control method, the UCC24630 is ideal for flyback power supplies over a wide-output voltage range since the device is not connected directly to the MOSFET drain. The SR drive turn-off threshold is not dependent on the MOSFET RDS(on) which allows optimizing for maximum conduction time. Also secondary current ringing due to device and layout inductance does not affect the SR turn-off threshold.
The UCC24630 controller offers a programmable false-trigger filter, a frequency detector to automatically switch to standby mode during low power conditions and pin fault protections. The UCC24630 is compatible with DCM, TM and CCM operation.
The wide VDD operating range, wide programming range of the VPC voltage and blanking time, allows use in a variety of flyback converter designs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC24630 | SOT23 (6) | 2.92 mm x 1.30 mm |
Changes from * Revision (March 2015) to A Revision
PIN | I/O(1) | DESCRIPTION | |
NAME | NO. | ||
DRV | 4 | O | DRiVe is an output used to drive the gate of an external synchronous rectifier N-channel MOSFET switching transistor, with source pin connected to GND. |
GND | 5 | G | The GrouND pin is both the reference pin for the controller and the low-side return for the drive output. Special care should be taken to return all AC decoupling capacitors as close as possible to this pin and avoid any common trace length with analog signal return paths. |
TBLK | 3 | – | Time BLanK pin is used to select the blanking time of the VPC rising edge. A programmable range from 200 ns to 1 µs is available to prevent false detection of the primary on-time due to ringing during DCM operation. |
VDD | 6 | P | VDD is the bias supply input pin to the controller. A carefully placed bypass capacitor to GND is required on this pin. |
VPC | 1 | I | The Voltage during Primary Conduction pin is connected to a resistor divider from the SR MOSFET drain. This pin determines a sample of the primary-side MOSFET volt seconds during the primary on-time. This voltage programs a voltage controlled current source for the internal VPC ramp charging current. |
VSC | 2 | I | The Voltage during Secondary Conduction pin is connected to a resistor divider from the power-supply output. This pin determines a sample of the secondary-side output voltage used to determine SR MOSFET conduction time. This voltage programs a voltage controlled current source for the internal VSC ramp charging current. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VVDD | Bias supply voltage, VDD | –0.3 | 30 | V | |
IDRV | Continuous gate current sink, DRV | 50 | mA | ||
IDRV | Continuous gate current source, DRV | –50 | mA | ||
IVPC | Peak VPC pin current | –1.2 | mA | ||
VDRV | Gate drive voltage at DRV | –0.3 | Self limiting | V | |
VVPC, VVSC | Voltage range, VPC, VSC | –0.3 | 4.5 | V | |
TJ | Operating junction temperature range | –55 | 150 | °C | |
TL | Lead temperature 0.6 mm from case for 10 seconds | 260 | °C | ||
TSTG | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VVDD | Bias supply operating voltage | 3.75 | 28 | V |
CVDD | VDD bypass capacitor | 0.47 | µF | |
TJ | Operating junction temperature | -40 | 125 | °C |
VVPC, VVSC | Operating Range | –0.3 | 2.3 | V |
THERMAL METRIC(1) | UCC24630 | UNIT | |
---|---|---|---|
DBV (6 Pins) | |||
RθJA | Junction-to-ambient thermal resistance | 180 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 71.2 | |
RθJB | Junction-to-board thermal resistance | 44 | |
ψJT | Junction-to-top characterization parameter | 5.1 | |
ψJB | Junction-to-board characterization parameter | 13.8 |
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY INPUT | ||||||
IRUN | Supply current, run | IDRV = 0, run state, FSW = 0 kHz | 0.9 | 1.2 | mA | |
ISTBY | Supply current, standby | IDRV = 0, standby mode | 110 | 160 | µA | |
UNDER-VOLTAGE LOCKOUT | ||||||
VVDD(on) | VDD turn-on threshold | VVDD low to high | 3.9 | 4 | 4.3 | V |
VVDD(off) | VDD turn-off threshold | VVDD high to low | 3.3 | 3.6 | 3.7 | V |
DRV | ||||||
RDRVLS | DRV low-side drive resistance | IDRV = 100 mA | 1 | 2 | Ω | |
VDRVST | DRV pull down in start-up | VDD= 0 to 2 V, IDRV= 10 µA | 0.95 | V | ||
VDRCL | DRV clamp voltage | VVDD = 30 V | 11 | 13 | 15 | V |
VPMOS | Disable PMOS high-side drive | VDD voltage to disable rail-to-rail drive, VDD rising | 9.3 | 10 | 10.5 | V |
VPMOS-HYS | PMOS enable hysteresis | VDD voltage hysteresis to enable rail to rail drive, VDD falling | 0.75 | 1 | 1.25 | V |
VDRHI | DRV pull-up high voltage | VVDD = 5 V, IDRV = 15 mA | 4.6 | 4.75 | 5 | V |
VSC INPUT | ||||||
VVSCEN | SR enable voltage | VVSC > VVSCEN, VVSC rising | 250 | 300 | 340 | mV |
VVSC-HYS | SR enable hysteresis | VVSC falling | 50 | mV | ||
VVSCDIS | SR disable voltage | 220 | 280 | mV | ||
IVSC | Input bias current | VVSC = 2 V | –0.25 | 0 | 0.4 | µA |
VPC INPUT | ||||||
VVPCEN | SR enable voltage | VVPCEN < VVPC | 345 | 400 | 450 | mV |
VVPCDIS | VPC threshold to disable SR | VVPC > VVPCDIS | 2.6 | 2.85 | 3.1 | V |
VVPC-TH | Threshold of VVPC rising edge | VVPC = 0.95 V, VVPC-TH = 0.85 x VVPC previous cycle | 0.76 | 0.808 | 0.86 | V |
VVPC-TH-CLP | Clamp threshold of VVPC rising edge | VVPC = 2 V | 0.9 | 1 | 1.1 | V |
IVPC | Input bias current | VVPC = 2 V | –0.25 | 0 | 0.4 | µA |
CURRENT EMULATOR | ||||||
RatioVPC_VSC | KVPC/KVSC | VVPC = 1.25 V, tVPC = 1 µs, VVSC = 1.25 V |
3.97 | 4.17 | 4.35 | |
VVPC = 1.25 V, tVPC = 5 µs, VVSC = 1.25 V |
3.95 | 4.17 | 4.37 | |||
VVPC = 2 V, tVPC = 1 µs, VVSC = 1.25 V |
3.85 | 4.09 | 4.26 | |||
VVPC = 1.25 V, tVPC = 1 µs, VVSC = 0.45 V |
3.85 | 4.07 | 4.28 | |||
CCM DEAD TIME | ||||||
KCCM-FAULT | If tSW (N+1) > tSW (N) x KCCM-FAULT, disable SR | 140% | 150% | 165% | ||
nCCM-FLT | Number of cycles to exit CCM fault if tSW (N+1) < tSW (N) x KCCM-FAULT | 4 | ||||
STANDBY OPERATION | ||||||
nENTO | Number of switching cycles to enter standby operation during tENTO | 64 | ||||
nEN | Number of switching cycles to exit standby operation during tEN(1) | 32 | ||||
OVER TEMPERATURE PROTECTION | ||||||
T(STOP) | Thermal shutdown temperature | Internal junction temperature | 165 | °C |
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DRV | ||||||
tR | DRV high-side rise time | VVDD = 12 V, CL = 3.3 nF, VDRV = 2 V to 8 V | 27 | 54 | ns | |
VVDD = 5 V, CL = 3.3 nF, VDRV = 1 V to 4 V | 50 | 100 | ns | |||
tF | DRV low-side fall time | VVDD = 12 V, CL = 3.3 nF, VDRV = 8 V to 2 V | 20 | 54 | ns | |
VVDD = 5 V, CL = 3.3 nF, VDRV = 4 V to 1 V | 15 | 50 | ns | |||
tDRVON | Propagation delay to DRV High | VVPC = 1 V to –0.05 V falling to DRV high, VVDD = 12 V, VDRV = 0 V to 2 V |
80 | 160 | ns | |
tDRVOFF | Propagation delay to DRV Low | Test mode | 65 | 95 | ns | |
VPC Input | ||||||
tVPC-SPL | VPC sampling time window | 81 | 100 | 125 | ns | |
tVPC-BLK | Minimum VPC pulse for SR DRV operation | RTBLK = 5 kΩ | 169 | 203 | 239 | ns |
RTBLK = 50 kΩ | 0.87 | 1.04 | 1.2 | µs | ||
SR On Control | ||||||
tSRONMIN | SR minimum on time after VPC falling. | 300 | 350 | 425 | ns | |
tOFF | SR off blanking time from DRV falling. | 2.35 | 2.5 | 2.65 | us | |
CCM Dead Time | ||||||
tCCMDT | SR turn-off dead time in CCM cycle limit | FSW = 100 kHz, RTBLK = 50 kΩ (1 µs tVPC-BLK setting) |
500 | 600 | 700 | ns |
Standby Operation | ||||||
tENTO | Time to disable SR operation, enter standby | Time to disable DRV | 11.5 | 12.8 | 14.1 | ms |
tEN | Time to enable SR operation, exit standby operation | Time to enable DRV(1) | 2.3 | 2.56 | 2.82 | ms |
VVPC = 1.25 V | tVPC = 1 µs | VVSC = 1.25 V |
VVPC = 12 V | tVPC = 2 µs |
RTBLK = 50 kΩ |
VVSC = 1.25 V | tVPC × VVPC = 3 V-µs |
RTBLK = 5 kΩ |
Fsw = 100 kHz | RTBLK = 50 k |