9.1 Application Information

The UCC24636 is a high performance controller driver for N-channel MOSFET power devices used for secondary-side synchronous rectification. The UCC24636 is designed to operate as a companion device to a primary-side controller to help achieve efficient synchronous rectification in switching power supplies. The controller features a high-speed driver and provides appropriately timed logic circuitry that seamlessly generates an efficient synchronous rectification system. With its current emulator architecture, the UCC24636 has enough versatility to be applied in DCM and TM operation. The UCC24636 SR on-time adjustability allows optimizing for PSR and SSR applications. Additional features such as pin fault protection, dynamic VPC threshold sensing, and voltage sense blanking time and make the UCC24636 a robust synchronous controller.

9.2 Typical Application

9.2.1 AC-to-DC Adapter, 5 V, 15 W

This design example describes the design of a 15-W off-line flyback converter providing 5 V at 3-A maximum load and operating from a universal AC input. The design uses the UCC28740 AC-to-DC valley-switching primary-side controller in a DCM type flyback converter and achieves over 86% full-load efficiency with the use of the secondary side UCC24636 synchronous rectifier controller.

• The design requirements are detailed in Design Requirements
• The design procedure for selecting the component circuitry for use with the UCC24636 is detailed in Calculation of Component Values.
• Test results shown in Application Waveforms And Curves highlight the unique advantages of using the UCC24636.

Figure 18. AC-to-DC Charger: 5 V, 15 W 

9.2.3 Calculation of Component Values

Figure 19. UCC24636 Circuit Design

For ease of understanding, Figure 19 is a modified version of Figure 15 where the component reference designators are the same as the schematic drawing of Figure 18.

9.2.3.1 VPC Input

For designs operating in constant current (CC) with low V_OUT, there are two cases to examine. At maximum power, V_IN(MIN) will be lower but V_OUT is nominal. In constant current operation, V_OUT is the minimum but V_IN(MIN) will be higher. Determine R9 for both conditions, and choose the lowest value.

For minimal power dissipation, select:

Equation 8.

Equation 9.

With R9 = 147 kΩ :

Equation 10.

Therefore, V_VPC is within the recommended range of 0.45 V to 2.2 V.

9.2.3.2 VSC Input

The value of R23 is recommended to be with the range of 25 kΩ to 50 kΩ.

There is a 10% margin included for the initial value calculation of R11 to provide timing margin during initial operation verification.

Equation 11.

With R11 = 115 kΩ, the operating range of the VSC pin is:

Equation 12.

Equation 13.

Therefore, V_VSC is within the recommended range of 0.3 V to 2.2 V.

The UCC24636 SR timing can be optimized (SR on time increased) by increasing the R115 value after initial operation confirmation. The Ratio_{VPC_VSC} parameter has a positive tolerance of 5.3%. Using 1% divider resistors for VPC and VSC should allow reducing the 10% initial SR timing margin.

9.2.3.3 TBLK Input

The blanking time is set with resistor R22.

Select the blanking time to meet the following criteria based on 660-ns minimum primary on-time at high line.

t_VPC-BLK = (t_PRI × 0.85) – 120 ns

spacer

Equation 14.

A value of R22 = 20 kΩ results in a blanking time of approximately 460 ns.

9.2.4 Application Waveforms And Curves

CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div

CH3 (Mag): VOUT, 2V/Div

CH4 (Green): DRV signal to Q1, 10V/Div

Figure 20. DRV Timing at 115 V_AC, 5 V, 3 A

CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div

CH3 (Mag): VOUT, 2V/Div

CH4 (Green): DRV signal to Q1, 10V/Div

Figure 22. DRV Timing at 115 V_AC, 5 V, 300 mA

Figure 24. Efficiency vs Output Current

CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div

CH3 (Mag): VOUT, 2V/Div

CH4 (Green): DRV signal to Q1, 10V/Div

Figure 21. DRV Timing at 230 V_AC, 5 V, 3 A

CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div

CH3 (Mag): VOUT, 2V/Div

CH4 (Green): DRV signal to Q1, 10V/Div

Figure 23. DRV Timing at 115 V_AC, 1.8 V, 3.3 A

Figure 25. Output Voltage vs Output Current

9.3 Do's and Don'ts

• Do operate the device within the recommended operating maximum parameters. Consider output overvoltage conditions when determining stress.
• Do consider the guideline for setting the blanking time resistor value illustrated in Figure 16.
• Do not use the UCC24636 in CCM flyback converter designs. For CCM designs, use the UCC24630 with the CCM dead time control function.
• Do not use the UCC24636 in LLC converters as they can operate in CCM.
• Do not add capacitance to the TBLK pin.
• Do not add significant external capacitance to the VPC pin as there will be increased delay of the signal. If filtering is necessary a recommended maximum capacitance is 15 pF with a lower resistor divider network value of 10 kΩ.