SLUSCG2A March   2016  – March 2016 UCC24636

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start Up and UVLO
      2. 8.3.2 Volt-Sec SR Driver On-Time Control
      3. 8.3.3 Standby Operation
      4. 8.3.4 Pin Fault Protection
        1. 8.3.4.1 VPC Pin Overvoltage
        2. 8.3.4.2 VPC Pin Open
        3. 8.3.4.3 VSC Pin Open
        4. 8.3.4.4 TBLK Pin Open
        5. 8.3.4.5 VPC and VSC Short to Ground
        6. 8.3.4.6 TBLK Pin Short to Ground
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up
      2. 8.4.2 Normal Operation
      3. 8.4.3 Standby Operation
      4. 8.4.4 Conditions to Stop Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 AC-to-DC Adapter, 5 V, 15 W
      2. 9.2.2 Design Requirements
      3. 9.2.3 Calculation of Component Values
        1. 9.2.3.1 VPC Input
        2. 9.2.3.2 VSC Input
        3. 9.2.3.3 TBLK Input
      4. 9.2.4 Application Waveforms And Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 VDD Pin
      2. 11.1.2 VPC Pin
      3. 11.1.3 VSC Pin
      4. 11.1.4 GND Pin
      5. 11.1.5 TBLK Pin
      6. 11.1.6 DRV Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Definition of Terms (For Design Example)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VVDD Bias supply voltage, VDD –0.3 30 V
IDRV Continuous gate current sink, DRV 50 mA
IDRV Continuous gate current source, DRV –50 mA
IVPC Peak VPC pin current –1.2 mA
VDRV Gate drive voltage at DRV –0.3 Self-limiting V
VVPC, VVSC Voltage range, VPC, VSC –0.3 4.5 V
TJ Operating junction temperature range –55 150 °C
TL Lead temperature 0.6 mm from case for 10 seconds 260 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VVDD Bias supply operating voltage 3.75 28 V
CVDD VDD bypass capacitor 0.22 µF
TJ Operating junction temperature -40 125 °C
VVPC, VVSC Operating range –0.3 2.2 V

7.4 Thermal Information

THERMAL METRIC(1) UCC24636 UNIT
DBV (SOT23)
6 PINS
RθJA Junction-to-ambient thermal resistance 180 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 71.2 °C/W
RθJB Junction-to-board thermal resistance 44 °C/W
ψJT Junction-to-top characterization parameter 5.1 °C/W
ψJB Junction-to-board characterization parameter 13.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature, VDD = 12 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY INPUT
IRUN Supply current, run IDRV = 0, run state, FSW = 0 kHz 0.9 1.2 mA
ISTBY Supply current, standby IDRV = 0, standby mode 110 160 µA
UNDER-VOLTAGE LOCKOUT
VVDD(on) VDD turn-on threshold VVDD low to high 3.9 4 4.3 V
VVDD(off) VDD turn-off threshold VVDD high to low 3.3 3.6 3.7 V
DRV
RDRVLS DRV low-side drive resistance IDRV = 100 mA 1 2 Ω
VDRVST DRV pull down in start-up VDD= 0 to 2 V, IDRV= 10 µA 0.95 V
VDRCL DRV clamp voltage VVDD = 30 V 11 13 15 V
VPMOS Disable PMOS high-side drive VDD voltage to disable rail-to-rail drive, VDD rising 9.3 10 10.5 V
VPMOS-HYS PMOS enable hysteresis VDD voltage hysteresis to enable rail to rail drive, VDD falling 0.75 1 1.25 V
VDRHI DRV pull-up high voltage VVDD = 5 V, IDRV = 15 mA 4.6 4.75 5 V
VSC INPUT
VVSCEN SR enable voltage VVSC > VVSCEN, VVSC rising 250 300 340 mV
VVSC-HYS SR enable hysteresis VVSC falling 50 mV
VVSCDIS SR disable voltage 220 250 280 mV
IVSC Input bias current VVSC = 2 V –0.25 0 0.4 µA
VPC INPUT
VVPCEN SR enable voltage VVPCEN < VVPC 345 400 450 mV
VVPCDIS VPC threshold to disable SR VVPC > VVPCDIS 2.6 2.85 3.1 V
VVPC-TH Threshold of VVPC rising edge VVPC = 0.95 V, VVPC-TH = 0.85 x VVPC previous cycle 0.76 0.808 0.86 V
VVPC-TH-CLP Clamp threshold of VVPC rising edge VVPC = 2 V 0.9 1 1.1 V
IVPC Input bias current VVPC = 2 V –0.25 0 0.4 µA
CURRENT EMULATOR
RatioVPC_VSC KVPC/KVSC VVPC = 1.25 V, tVPC = 1 µs,
VVSC = 1.25 V		 3.97 4.17 4.35
VVPC = 1.25 V, tVPC = 5 µs,
VVSC = 1.25 V		 3.95 4.17 4.37
VVPC = 2 V, tVPC = 1 µs,
VVSC = 1.25 V		 3.85 4.09 4.26
VVPC = 1.25 V, tVPC = 1 µs,
VVSC = 0.45 V		 3.85 4.07 4.28
STANDBY OPERATION
nENTO Number of switching cycles to enter standby operation during tENTO 64
nEN Number of switching cycles to exit standby operation during tEN(1) 32
OVER TEMPERATURE PROTECTION
T(STOP) Thermal shutdown temperature Internal junction temperature 165 °C
(1) The device exits standby operation as soon as nEN occurs within tEN.

7.6 Timing Requirements

over operating free-air temperature range, VDD = 12 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
DRV
tR DRV high-side rise time VVDD = 12 V, CL = 3.3 nF, VDRV = 2 V to 8 V 27 54 ns
VVDD = 5 V, CL = 3.3 nF, VDRV = 1 V to 4 V 50 100
tF DRV low-side fall time VVDD = 12 V, CL = 3.3 nF, VDRV = 8 V to 2 V 20 54 ns
VVDD = 5 V, CL = 3.3 nF, VDRV = 4 V to 1 V 15 50
tDRVON Propagation delay to DRV High VVPC = 1 V to –0.05 V falling to DRV high,
VVDD = 12 V, VDRV = 0 V to 2 V		 80 160 ns
tDRVOFF Propagation delay to DRV Low Test mode 65 95 ns
VPC INPUT
tVPC-SPL VPC sampling time window 81 100 125 ns
tVPC-BLK Minimum VPC pulse for SR DRV operation RTBLK = 5 kΩ 169 203 239 ns
RTBLK = 50 kΩ 0.85 1.01 1.18 µs
SR ON CONTROL
tSRONMIN SR minimum on time after VPC falling. 300 350 425 ns
tOFF SR off blanking time from DRV falling. 3.96 4.35 4.75 us
STANDBY OPERATION
tENTO Time to disable SR operation, enter standby Time to disable DRV 11.5 12.8 14.1 ms
tEN Time to enable SR operation, exit standby operation Time to enable DRV(1) 2.3 2.56 2.82 ms
(1) The device exits standby operation as soon as nEN occurs within tEN.

7.7 Typical Characteristics

VVDD = 12 V, TJ = 25°C, unless otherwise noted.
UCC24636 C001_.png
Figure 1. VDD Turn-On and Turn-Off Threshold vs Temperature
UCC24636 C003_.gif
Figure 3. VPC Enable Threshold vs Temperature
UCC24636 C005_.png
VVPC = 1.25 V tVPC = 1 µs VVSC = 1.25 V
Figure 5. VPC-to-VSC Ramp Gain Ratio vs Temperature
UCC24636 C007_.png
VVPC = 1.25 V tVPC = 2 µs
Figure 7. VPC-to-VSC Ramp-Gain Ratio vs VSC Voltage
UCC24636 C009_.png
RTBLK = 50 kΩ
Figure 9. VPC Blanking Time vs Temperature (Maximum Setting)
UCC24636 D013_SLUSCG2.gif
Figure 11. DRV Minimum Off Time vs Temperature
UCC24636 C002_.png
Figure 2. Standby Current vs Temperature
UCC24636 C004_.png
Figure 4. VSC Enable Threshold vs Temperature
UCC24636 C006_.png
VVSC = 1.25 V tVPC × VVPC = 3 V-µs
Figure 6. VPC-to-VSC Ramp-Gain Ratio vs VPC Voltage
UCC24636 C008_.png
RTBLK = 5 kΩ
Figure 8. VPC Blanking Time vs Temperature (Minimum Setting)
UCC24636 C011_.png
Figure 10. DRV Minimum On Time vs Temperature